{"id":1474578,"url":"https://alion.io/job/intel-corporation-senior-lithography-and-photomask-process-engineer","title":"Senior Lithography and Photomask Process Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":94,"ghost_share":0.032,"stale_share":0.564,"repost_share":0.043,"time_to_fill_p50_days":30,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Semiconductors","role_family":"Semiconductors","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Leixlip, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":104000,"max_usd":204000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":107},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Design of Experiments","optional":false},{"name":"EUV","optional":false},{"name":"JMP","optional":false},{"name":"MATLAB","optional":false},{"name":"Photolithography","optional":false},{"name":"Python","optional":false},{"name":"Statistical Process Control","optional":false}],"status":"live","first_seen_at":"2026-09-29T18:18:51Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-11-03T12:22:44Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"Job Details:\nJob Description:\nKey Responsibilities:\nPhotomask and Reticle Operations: Oversee photomask incoming quality control, pellicle integrity, reticle qualification protocols, and reticle lifecycle management across advanced EUV and DUV toolsets.\nAdvanced Pellicle Development: Drive next gen EUV pellicle development, material optimization for enhanced transmission, stability, defect mitigation and overall yield improvement. Optimize reticle usage, inspection and disposition strategies over life cycle.\nCross-Functional Process Integration: Partner closely with Scanner/Litho teams, Reticle Design, Thin Films, Etch, and Yield Enhancement engineering teams to diagnose patterning excursions and accelerate technology transitions.\nYield Ramp and Excursion Containment: Lead root cause failure analysis (RCFA) for yield-limiting lithography and reticle-related defects during new process node development and high-volume manufacturing (HVM).\nTechnical Mentorship and Industry Engagement: Provide technical leadership to junior and mid-level process engineers, establish standard operating procedures (SOPs), and collaborate directly with leading lithography and mask equipment suppliers.\nQualifications:\nEducation: M.S. with 8+ years of foundry experience or Ph.D. of Foundry experience in Electrical Engineering, Chemical Engineering, Materials Science, Physics, Optics, Microelectronics, or a related semiconductor engineering discipline.\nExperience: 8+ years of hands-on process engineering experience in advanced semiconductor lithography and photomask/reticle technologies within high-volume manufacturing (HVM) or advanced technology development fabs.\nPhotomask and Reticle Expertise: In-depth knowledge of mask fabrication, mask metrology, aerial image modeling, pellicle technology, reticle degradation mechanisms, and mask defect inspection platforms.\nLithography Toolset and Process Knowledge: Proven proficiency across DUV (ArFi / 193nm immersion) and EUV exposure systems (ASML Twinscan / NXE platforms), track integration, and advanced CD metrology.\nAnalytical and Statistical Mastery: Advanced proficiency with Statistical Process Control (SPC), Design of Experiments (DOE), yield analytics platforms, JMP, Python, or MATLAB for complex data modeling and multivariate analysis.\nLeadership and Communication: Track record of driving cross-functional taskforces, writing comprehensive technical documentation, and delivering executive briefings on process yield, tool performance, and quality enhancements.\nWe invite you to bring your technical expertise and innovative vision to Intel Foundry, where your work will drive the next generation of semiconductor technology. Join us to make an impact and advance your career in a dynamic, collaborative environment.\nJob Type:\nExperienced HireShift:\nShift 1 (Ireland)Primary Location:\nIreland, LeixlipAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AEU Salary\nWe offer a total compensation package that ranks among the best in the industry.\nAnnual Salary Range for this job which could be performed in Ireland is: €103,000.00 - €161,000.00\n\nThe compensation range displayed in this posting reflects the minimum and maximum target compensation for this position. Within this range, individual pay is determined by job related skills, experience, and relevant education, training. As part of our total compensation approach, the final offer may include additional pay components and benefits. Your recruiting team will share the confirmed base salary along with any applicable total compensation elements upon employment offer delivery.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*","description_format":"text","description_chars":4320,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"Ireland","iso":"IE","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-29T18:18:51Z"}],"visa":[],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.593,"p_room":0.55,"age_days":34,"expected_fill_days":30,"reasons":["conf:3","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-senior-lithography-and-photomask-process-engineer","json_url":"https://alion.io/job/intel-corporation-senior-lithography-and-photomask-process-engineer.json","meta":{"generated_at":"2026-11-03T17:18:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24100,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-corporation-senior-lithography-and-photomask-process-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-corporation-senior-lithography-and-photomask-process-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-corporation-senior-lithography-and-photomask-process-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-corporation-senior-lithography-and-photomask-process-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-corporation-senior-lithography-and-photomask-process-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1474578}},{"tool":"search_jobs","arguments":{"company":"intel.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1474578},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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