{"id":1164477,"url":"https://alion.io/job/intel-corporation-senior-physical-design-engineer","title":"Senior Physical Design Engineer","company":{"id":35,"name":"Intel Corporation","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":49,"ghost_share":0,"stale_share":0.714,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-09-24T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":115000,"max_usd":218000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":2148},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Ruby","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-09-23T00:00:00Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-09-24T18:22:24Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Details:\nJob Description:\nAbout the Role\nJoin a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies.\nWhat You’ll Do\nKey responsibilities will include but not limited to:\nOwn physical design and implementation of CPU core blocks or subsystems\nExecute synthesis, floorplanning, place and route, and design closure\nPerform static timing analysis (STA), power analysis, and physical verification\nDrive convergence of timing, power, and area (PPA) metrics\nDebug and resolve complex design issues across multiple design stages\nDevelop and optimize design flows and automation scripts\nCollaborate cross-functionally with RTL design, verification, clocking, and full-chip teams\nContribute to improving design methodologies and best practices\nProvide guidance to junior engineers where applicable\nBehavioral traits that we are looking for:\nStrong problem-solving and analytical thinking\nTakes ownership and accountability for deliverables\nCollaborates effectively across multidisciplinary teams\nCommunicates technical concepts clearly and concisely\nPrioritizes work effectively in a fast-paced environment\nContinuously learns and applies new tools and methodologies\nWhy Join Us\nWork on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide\nBe part of a team driving innovation at advanced semiconductor process nodes\nContribute across the full RTL-to-GDS flow, gaining exposure to complex, high-impact silicon design\nCollaborate with experienced engineers across architecture, design, and full-chip integration\nGrow your technical expertise through challenging problems, modern tools, and continuous learning opportunities\nJoin a culture that values inclusion, collaboration, and diverse perspectives while delivering industry-leading technology\nIntel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. \n\nQualifications:\nQualifications\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nNote:\nFor information on Intel’s immigration sponsorship guidelines, please see\nIntel U.S. Immigration Sponsorship Information\nMinimum Qualifications and Experience:\nBachelors in Computer / Electrical Engineering or related field with 7+ years of relevant work experience. Or a Masters in the same field with 4+ years of relevant work experience.\nYour experience described above must be in the following:\nExperience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure\nPV convergence (including static timing and power analysis)\nChip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.\nScripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)\nExperience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP\nPreferred Qualifications and Experience:\nIndustry experience/exposure with CPU Micro-Architecture\nPhysical design best known practices concerning floor-planning, routing techniques, clock distribution\nStatic Timing Analysis, Noise analysis, and reliability verification techniques\nRTL to GDS methodologies and formal equivalence\nSynopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":5925,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Manufacturing","Semiconductor Manufacturing","Computer Components"],"lifecycle":[{"event":"open","at":"2026-09-24T01:45:54Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":28,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-09-24T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/intel-corporation-senior-physical-design-engineer","json_url":"https://alion.io/job/intel-corporation-senior-physical-design-engineer.json","meta":{"generated_at":"2026-09-24T21:53:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"subnet","units_charged":1,"used_today":170,"day_limit":5000,"remaining_today":4830,"minute_limit":60,"resets_at":"2026-09-25T00:00:00Z"}}}