{"id":185352,"url":"https://alion.io/job/intel-corporation-senior-standard-cell-library-engineer","title":"Senior Standard Cell Library Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":92,"ghost_share":0.033,"stale_share":0.5,"repost_share":0.043,"time_to_fill_p50_days":30,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Folsom, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":155000,"max_usd":286000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":true},{"name":"Cadence Pegasus","optional":true},{"name":"Cadence Tempus","optional":true},{"name":"Cadence Virtuoso","optional":true},{"name":"Python","optional":true},{"name":"Siemens Calibre","optional":true},{"name":"Synopsys Custom Compiler","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys HSPICE","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys StarRC","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2026-09-01T14:35:42Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-30T13:46:17Z","board_verified":true,"closed_at":null,"days_open":59,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":57},"description":"Job Details:\nJob Description:\nAbout the Organization\nIntel's Foundry Standard Cellteam is seekinga talented and motivated Senior Design Engineerto join our growing team. In this role, you will designleading edge experimentstodevelop, characterize, and teststandard cells.You will play a critical role in enabling customersbylistening to their needs and buildingthe solutions.\nKey Responsibilities\nDefines, implements, characterizes, and validatesdesign solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost. \nCapable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability to achieve goals. \nCollaborates closely with all standard cell collateralto understand design requirements and develop robust implementation and validation strategies. \nReviews and validateswork toensurecompliance with design, manufacturing, and quality requirements. \nFast turn-around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders). \nRun end-to-end flows to generate, validate, and release custom standard cell collateral per on demand requests.\nCore Competencies\nStrong written and verbal communication skills are requiredwith the ability to tailor the communicationbased on the audience.\nQualifications:\nThe Minimum qualifications listed below are requiredto be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimumrequirements and are considered a plus factor in identifyingtop candidates.\nMinimum Qualifications:\nBachelor's degree in:Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering,or a STEMrelated field.\n2+ years' experience in one or more of the following: Standard cell layout \nStandard cell abstract modeling \nStandard cell characterization \nASIC design and verification \n\nExperience using one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre.\nPreferred Qualifications:\nPost Graduate Degree in:Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering,or a STEMrelated field.\nUnix proficiencyand basic software skills using command line languages (csh, bash, perl, python) are highly valued.\nWe are looking for innovative thinkers ready to make an impact inthe evolving semiconductor landscape. Apply today and be part of Intel's mission to create technologies that connect and enrich lives globally.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, California, Santa ClaraAdditional Locations:\nUS, California, FolsomPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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