{"id":2985936,"url":"https://alion.io/job/intel-dft-design-engineering-intern","title":"DFT Design Engineering Intern","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":88,"ghost_share":0.034,"stale_share":0.523,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false}],"status":"live","first_seen_at":"2026-10-20T00:00:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T03:51:18Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Details:\nJob Description:\nIn this position, you will be involving in the training, design and development of next generation SOC by using AI for wide range of Intel products. Your responsibilities will include one or some of the following but not limited to:\nPerform evaluation and development of new DFT test methodology to meet guaranteed specification and screen defects on silicon which meets Intel's product quality commitment\nAssist DFT Engineers in implementation of defined DFT architecture.\nUse CAD tool extensively to simulate logic behavior and circuit performance\nUnderstand VLSI Structural Design methodology and automate design flows\nImplement DFT designs within the confines of structural and physical parameters, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration.\nDeveloping AI capabilities for the above items that includes AI skills, agent and building agentic AI flow.\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position:\nCurrently pursuing Bachelor of Science degree in Electrical Engineering and/or Computer Engineering and/or Computer Science or a Masters of Science degree in Electrical Engineering and/or Computer Engineering and/or Computer Science\nGood communication skills and proficient in English\nKnowledge on Unix, VLSI Design, SOC/PC Architecture, System Verilog, DFT Methodologies is major plus\nJob Type:\nStudent / InternShift:\nShift 1 (Malaysia)Primary Location:\nMalaysia, PenangAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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