{"id":3001800,"url":"https://alion.io/job/intel-e-core-cpu-clock-design-engineer","title":"E-core CPU Clock Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":88,"ghost_share":0.034,"stale_share":0.523,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":51000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":true},{"name":"Cadence Conformal","optional":true},{"name":"Siemens Calibre","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"TCL Scripting","optional":true}],"status":"live","first_seen_at":"2026-10-14T00:00:00Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-24T03:51:18Z","board_verified":false,"closed_at":null,"days_open":12,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":12},"description":"Job Details:\nJob Description:\nJoin a Team That Defines the Heartbeat of Next-Generation CPUs.Intel is seeking passionate engineers to help develop the clocking architecture that powers our next-generation CPU products. Whether you're a college graduate eager to launch your career or an experienced engineer ready to solve some of the industry's most complex technical challenges, you'll have the opportunity to work on cutting-edge semiconductor technologies that impact millions of devices worldwide.\nAs a CPU Clock Design Engineer you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.\nWhat You'll Do\nResponsibilities may include, but are not limited to:\nDesign, implement, and optimize clock distribution networks for high-performance CPU and SoC products.\nContribute to clock architecture development and clock tree synthesis (CTS) methodologies.\nPerform timing analysis and support timing closure across complex semiconductor designs.\nDevelop custom circuits, library cells, and clock-related design solutions.\nAnalyze performance, power, area, and timing tradeoffs to improve product efficiency.\nCreate automation solutions using scripting and programming languages to improve design productivity.\nCollaborate closely with architecture, design, physical implementation, validation, and EDA teams.\nSupport debug, validation, and optimization activities throughout the product development lifecycle.\nDrive technical issues to closure while maintaining high-quality engineering standards.\nInfluence future methodologies, design flows, and clocking technologies.\nBehavioral Traits We Are Looking For\nStrong ownership and accountability for technical deliverables.\nCuriosity and passion for solving complex engineering challenges.\nEffective problem-solving and analytical thinking skills.\nAbility to collaborate across multiple engineering disciplines.\nStrong communication skills with both technical and non-technical stakeholders.\nAdaptability and willingness to learn new tools, technologies, and methodologies.\nAbility to balance multiple priorities in a fast-paced environment.\n• Continuous focus on quality, execution, and innovation.\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum qualifications:\nMust have either BS or MS in Electrical Engineering or Computer Engineering.\nMinimum 6 year of experience in:\nCPU Clock Design.\nCPU physical design and timing verification.\nSynthesis/APR flows on multi voltage high frequency designs including custom polygon editing.\nTcl scripting.\nNoise, cross-talk, OCV analysis.\nFloorplanning and physical design and timing closure.\nFormal equivalence, DRC/LVS, IR and electro-migration checks.\nPreferred qualifications:\n7+ years of experience with the above skill sets.\nExperience with Fusion Compiler, DCT, DCE, ICC2, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT.\nCadence Tools Experience Not a Must But Preferred.\nJob Type:\nExperienced HireShift:\nShift 1 (Malaysia)Primary Location:\nMalaysia, PenangAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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