{"id":2985939,"url":"https://alion.io/job/intel-logic-design-engineer","title":"Logic Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":104,"ghost_share":0.019,"stale_share":0.596,"repost_share":0.038,"time_to_fill_p50_days":27,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19500,"max_usd":45000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":775},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-20T00:00:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-21T12:24:14Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Details:\nJob Description:\nDevices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing technology that reaches people around the globe.\nKey Responsibilities\nOwn DDG internal IP RTL design and development or integrate high-performance and high-bandwidth IP into Client SoC platforms.\nDefine, implement, and deliver new IP features, change requests, and feature enhancements.\nDrive IP-to-SoC handoff quality, ensuring design completeness, compliance, and readiness for downstream integration.\nPerform logic and RTL integration into SoC, including power intent definition, signal handling across power planes and clock domains, and delivery of front-end collateral for system and software integration.\nDevelop design solutions and collaborate closely with verification teams to validate functionality, features, and integration readiness.\nExecute front-end quality checks across RTL static analysis, synthesizability, timing and power convergence, netlist quality, formal equivalence verification, and related design quality milestones.\nInterpret power specifications and translate power requirements into design considerations, analysis plans, and measurable checks.\nSupport power estimation, analysis, rollup, and convergence. Investigate power issues, identify root causes, and recommend design or flow solutions.\nQualifications:\nBachelor or Master Degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline, with at least 3 years of experience in IP or SoC RTL/Logic Design.\nStrong knowledge of one or more of the following areas:IP/subsystem architecture, I/O architecture, and industry-standard high-speed bus protocols.\nSoC/ASIC design methodology and industry-standard front-end development practices.\nSoC fabric and interconnect design.\nRTL design using Verilog and SystemVerilog.\nIndustry front-end and RTL tools, flows, and design methodologies.\nExperience using AI tools or AI-assisted engineering workflows to improve RTL/Logic development productivity, including design exploration, code generation, review, debug, documentation, and front-end quality checks.\nAbility to orchestrate efficient development workflows by combining domain expertise, automation, scripting, AI-assisted tools, and structured engineering practices to accelerate delivery while maintaining design quality.\nPre-silicon or post-silicon lab debug and power-on experience.\nExcellent communication, collaboration, problem-solving, and teamwork skills.\n\nJob Type:\nExperienced HireShift:\nShift 1 (Malaysia)Primary Location:\nMalaysia, PenangAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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