{"id":3753127,"url":"https://alion.io/job/intel-ltd-retopc-design-rule-and-technology-definition-engineer","title":"LTD RET/OPC Design Rule and Technology Definition Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":102,"ghost_share":0.029,"stale_share":0.539,"repost_share":0.059,"time_to_fill_p50_days":30,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Photolithography","optional":false},{"name":"Git","optional":true},{"name":"GitHub","optional":true},{"name":"GitLab","optional":true},{"name":"Knowledge Graph","optional":true},{"name":"LLM","optional":true},{"name":"Semantic Search","optional":true}],"status":"live","first_seen_at":"2026-11-03T00:00:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-05T21:06:59Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nIntel is in the middle of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. Join LTD and help create the next generation of technologies that will touch the lives of people the world over for decades to come.\nThe RET DR and Tech Def team uses current and future lithography manufacturing tools to drive Design and process Technology Co-optimization (DTCO) as well as Design For Yield (DFY) to enable advanced node definition and extend the limits of feature sizes that are patternable by Intel Foundry for semiconductor devices.\nQualifications:\nMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.\nMinimum Qualifications\nBachelor's degree in Computer Science, Software Engineering, Electrical Engineering, or a related field with 6+ years of professional experience with semiconductor industry technologies\nOR\nMaster's degree in Computer Science, Software Engineering, Electrical Engineering, or a related field with 4+ years of professional experience with semiconductor industry technologies\nOR\nPh.D. in Computer Science, Software Engineering, Electrical Engineering, or a related field with 2+ years of professional experience with semiconductor industry technologies\nProfessional hands-on experience with semiconductor industry technologies includes one or more of the following:\nExperience developing software, automation frameworks, data systems, or engineering infrastructure in a technical environment\nExperience designing and maintaining structured data models, metadata frameworks, databases, knowledge repositories, or configuration-managed data systems.\nExperience with source control and repository management systems (Git, GitLab, GitHub, or equivalent).\nExperience developing automation workflows, APIs, data pipelines, or software tools used by engineering teams.\nKnowledge of AI/LLM technologies and their application to engineering knowledge management, data extraction, workflow automation, and decision support.\nStrong problem-solving skills and ability to work across multiple technical disciplines. Highly motivated to improve Intel quality and in achieving customer trust.\nPreferred Qualifications\nExperience in the semiconductor industry\nUnderstanding of semiconductor physical design, layout methodologies, or design rule development\nExperience working with process design rules, patterning technologies, or DTCO methodologies\nExperience developing data and automation platforms that support semiconductor technology development\nExperience with graph databases, knowledge graphs, semantic search, vector databases, or AI-enabled knowledge repositories.\nFamiliarity with cloud-native software development, data orchestration frameworks, and modern software engineering practices\nFor information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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