{"id":3763497,"url":"https://alion.io/job/intel-memory-design-engineer","title":"Memory Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":102,"ghost_share":0.029,"stale_share":0.539,"repost_share":0.059,"time_to_fill_p50_days":30,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"junior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-02T00:00:00Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-05T15:18:54Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nIntel's Corporate Memory Organization (CMO) within Design Technology Platform (DTP) drives development of Memory Compilers on Intel's leading-edge process technologies. The organization is responsible for architecting, designing and delivering high-performance and energy-efficient embedded memory IP that maximize silicon performance, optimize density, and maximize manufacturing yield across Intel Products and Intel Foundry platforms.\nAs a Circuit Design Engineer in CMO, you will be responsible for architecting, designing, and delivering SRAM compilers across high-density (HD) and high-performance (HP) profiles. You will also collaborate with Intel’s Technology Development (TD) group on Design and Technology Co-Optimization (DTCO) to co-define the silicon process and physical layout rules.\nResponsibilities of the role include but are not limited to:\nProvide industry competitive SRAM design solutions to meet challenging memory design specs for various product segments.\nDesign, validation, and characterization of Memory Compilers.\nMemory Compiler Design Flow and Methodology development.\nBehavioral skills/traits as follow:\nInterfacing with customers.\nLogical thinking, analytical and problem-solving skills.\nVerbal/written communication skills.\nInterpersonal skills.\nMultitasking/prioritization skills.\nThis is an entry level position, and compensation will be given accordingly.\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience or coursework listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.\nThis position is not eligible for Intel immigration sponsorship.\n Minimum Qualifications:\nCandidate must have a MS degree with 6+ months of experience in Electrical Engineering or Computer Engineering or related field.\n6+ months of experience in the following: Scripting (Perl or tcl or Python, etc.)\nExperience with SRAM operations\nTransistor level operation (VLSI course work), design challenges under process variations and low power circuit technique.\nJob Type:\nCollege GradShift:\nShift 1 (United States of America)Primary Location:\nUS, Texas, AustinAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $91,150.00-172,860.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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