{"id":2985930,"url":"https://alion.io/job/intel-memory-signal-integrity-engineer","title":"Memory Signal Integrity Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":83,"ghost_share":0.036,"stale_share":0.518,"repost_share":0.048,"time_to_fill_p50_days":30,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Heredia, Costa Rica"],"countries":["CR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":85000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":769},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-20T00:00:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-27T11:10:49Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Details:\nJob Description:\nAs a Signal Integrity Engineer, you will play a pivotal role in delivering high-speed signal integrity solutions for complex platforms, boards, and packages. You will perform simulations, define signal integrity rules, and guide physical implementations to optimize design margins and ensure the integrity of next-generation interfaces. Your work on electrical specifications and interconnect designs will directly support Intel's cutting-edge products, ensuring they meet rigorous standards for performance and quality.\nYou will be joining the Silicon and Platform Engineering Group (SPE), which drives innovation by developing foundational technologies for Intel's products. This team focuses on designing and optimizing advanced silicon and platform solutions to deliver high-performance, scalable, and reliable technology. As part of this group, you will contribute to shaping the future of Intel's hardware and platform offerings.\nThe primary responsibilities for this role will include, but are not limited to:\nDevelop and deliver signal integrity solutions for high-speed interconnects in complex platforms, boards, and packages.\nPerform 2D and 3D modeling and simulations to evaluate electrical structures for die-to-die interconnects.\nDefine signal integrity rules, guide their implementation, and optimize design margins to enhance product performance.\nDesign, simulate, and characterize test structures to correlate simulations with real-world measurements using high-speed equipment.\nCollaborate with IP design and silicon integration teams to align designs with platform-level requirements, minimizing signal degradation and costs.\nGenerate electrical specifications and industry-standard interconnect guidelines to support next-generation interface development.\nDocument characterization reports and implementation guidelines for platform design improvements.\nQualifications:\nMinimum Qualifications:\nMinimum qualifications are required to be initially considered for this position.\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 0-1 years of hands-on experience in signal integrity, high-speed interconnect design, or related domains with demonstrated skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in Electrical Engineering, Computer Engineering, or a related field with no prior professional experience.\nKnowledge of signal integrity design and trade-offs, including attenuation, crosstalk, jitter, and power noise.\nExperience with simulation tools and high-speed equipment for signal integrity analysis.\nProficiency in developing and analyzing 2D and 3D models for electrical structures.\nFamiliarity with debugging interconnect challenges and improving design optimization.\nIntermediate to Advanced English proficiency (both verbal and written).\nMust have unrestricted - permanent right to work in Costa Rica.\nPreferred Qualifications:\nPreferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nStrong communication skills with the ability to collaborate effectively across teams.\nDemonstrated ability to solve complex technical problems and present solutions.\nExperience working on high-speed platforms, boards, or package designs.\nFamiliarity with industry standards and consortium activities for next-generation interface specifications.\nJoin Intel and be part of a team that is shaping the future of technology. Your expertise will drive innovation in signal integrity, empowering Intel's products to achieve excellence in performance and reliability.\nJob Type:\nExperienced HireShift:\nShift 1 (Costa Rica)Primary Location:\nCosta Rica, San JoseAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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