{"id":3157797,"url":"https://alion.io/job/intel-mixed-signal-ip-verification-engineer","title":"Mixed Signal IP Verification Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":124,"ghost_share":0.024,"stale_share":0.556,"repost_share":0.04,"time_to_fill_p50_days":24,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":21000,"max_usd":53000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true},{"name":"Verification & Validation","optional":true}],"status":"live","first_seen_at":"2026-10-23T15:03:27Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-23T23:12:28Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Details:\nJob Description:\nCome join Intel's Devices Development Group, responsible for creating leading Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a Mixed Signal IP Verification Engineer, ready to research, design, develop, and test Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.\nResponsibilities may include but not be limited to:\nPerform functional verification of Mixed Signal Power Delivery IPs (like Voltage Regulator, ADC, DAC) to ensure design meets specification.\nProactively and independently develop test plan, add stimuli, add checkers/assertions to ensure adequate coverage and verify compliance with IP microarchitecture specifications.\nCollaborate with RTL developers, Analog Design Engineers to improve verification of architectural and microarchitectural features.\nReplicate, root cause, and debug issues in the pre-silicon verification environment.\nDocument test plans and participate in technical reviews with design teams.\nLead or be willing to lead Mixed Signal Validation(MSV) activities by running AMS simulations, collaborate cross-functionally with design teams to identify, root-cause and resolve schematic bugs.\nMaintain and refine existing functional verification infrastructure and methodology for multiple IP generations.\nActively participate in defining the architecture and microarchitecture of the IP being developed.\nQualifications:\nYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications:\nMust have either a Bachelor's degree with 5+ years of experience or Master's degree with 3+ years of experience in Electrical Engineering or Computer Engineering\nMinimum 3 years of experience in Design Verification and Validation methodologies with UVM, System Verilog and industry standard EDA tools\nMinimum 3 years of hands-on experience working on Mixed Signal IPs and driving AMS activities\nMinimum 3 years of experience with reading and interpreting technical specs and Register Transfer Level (RTL) code and Behavioral Model (BMOD) code\nMinimum 3 years of experience with writing validation plans and implement those validation plans Preferred Qualifications:\nExperience with Design Verification of both Digital and Mixed Signal IPs \nStrong ability to communicate technical analysis and conclusions clearly to stakeholders\nExcellent self-organizing and time management skills\nProficient in using AI tools to boost automation and efficiency\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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