{"id":3168414,"url":"https://alion.io/job/intel-platform-hardware-design-engineer-3","title":"Platform Hardware Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":92,"ghost_share":0.033,"stale_share":0.5,"repost_share":0.043,"time_to_fill_p50_days":30,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":51000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":true},{"name":"Ansys SIwave","optional":true},{"name":"Cadence Allegro","optional":true},{"name":"Cadence Sigrity","optional":true},{"name":"OrCAD","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-22T00:00:00Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-30T16:10:35Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Job Details:\nJob Description:\nJob Description :Designs, develops, and delivers complex platform hardware solutions for Intel validation and product development platforms. Translates system and platform requirements into board-level electrical designs and drives implementation from architecture definition through board bring-up, validation, and debug.\nResponsible for leading the design and development of high-speed printed circuit boards (PCB), subsystems, and platform solutions while ensuring compliance with electrical, mechanical, thermal, manufacturability, and cost objectives.\nKey responsibilities include:\nIndependently design and develop complex platform hardware solutions including schematic capture, component selection, board-level architecture, and subsystem integration.\nTranslate platform requirements into detailed electrical specifications, schematics, placement constraints, routing requirements, and implementation guidelines.\nDevelop and review high-speed interface implementations including DDR, PCIe, USB, Ethernet, CXL, and other high-speed communication interfaces.\nDefine PCB stack-up requirements, impedance control strategies, return path optimization, power delivery implementation, and routing constraints.\nReview and approve schematics, component selections, and board-level implementations to ensure compliance with platform electrical requirements.\nConduct PCB layout and routing reviews, providing recommendations to improve signal integrity, power integrity, manufacturability, and overall design quality.\nGenerate and maintain platform design guidelines, routing rules, electrical specifications, and implementation best practices.\nPerform system-level electrical analysis including Signal Integrity (SI), Power Integrity (PI), timing analysis, and design margin assessments.\nCollaborate with PCB layout engineers, package engineers, architects, firmware developers, validation teams, and manufacturing partners to ensure successful platform implementation.\nLead board bring-up, electrical validation, root cause analysis, and debugging activities using advanced lab equipment.\nDrive issue resolution for complex hardware problems and recommend corrective actions.\nMentor junior engineers and provide technical guidance during design reviews and debug activities.\nContribute to continuous improvement of platform design methodologies, validation processes, and engineering best practices.\nThe ideal candidate should exhibit the following behavioral traits:\nStrong technical leadership and problem-solving abilities.\nExcellent verbal and written communication skills.\nAbility to drive technical discussions and influence design decisions.\nDemonstrated ownership and accountability for project execution.\nAbility to work effectively across global cross-functional teams.\nSelf-motivated with strong attention to detail and commitment to engineering excellence.\nStrong analytical mindset with a structured approach to debugging and root cause analysis.Qualifications:\nMinimum Qualifications\nBachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.\nMinimum 7+ years of relevant experience in platform hardware design, board design, electrical engineering, or related disciplines.\nStrong experience in schematic capture and complex PCB design.\nStrong knowledge of digital, analog, and mixed-signal circuit design.\nExperience developing and reviewing high-speed board-level implementations.\nWorking knowledge of Signal Integrity and Power Integrity principles.Thx y\nExperience performing board bring-up, validation, and hardware debugging.\nStrong understanding of high-speed interfaces and platform architectures.\nExperience using oscilloscopes, logic analyzers, protocol analyzers, and related laboratory equipment.\nIntermediate to advanced English communication skills.\nPreferred Qualifications\nExperience with PCB design tools such as Cadence Allegro, OrCAD, or Mentor Graphics.\nExperience defining routing constraints and PCB design guidelines.\nExperience reviewing and approving schematics and PCB layouts.\nStrong understanding of:\nPCIe Gen4/Gen5/Gen6\nDDR4/DDR5\nUSB4\nEthernet\nHigh-speed SerDes interfaces\nExperience performing SI/PI simulations using tools such as:\nCadence Sigrity\nAnsys HFSS\nSIwave\nSPICE-based simulators\nKnowledge of EMI/EMC design techniques and compliance requirements.\nFamiliarity with FPGA, CPLD, ASIC, and Intel platform architectures.\nExperience with DFM, DFT, and reliability methodologies.\nKnowledge of Python, automation scripting, or design workflow automation.\n• Experience mentoring engineers and leading technical design reviews.\nJob Type:\nExperienced HireShift:\nShift 1 (Malaysia)Primary Location:\nMalaysia, PenangAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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