{"id":3178569,"url":"https://alion.io/job/intel-platform-integration-engineer","title":"Platform Integration Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":83,"ghost_share":0.036,"stale_share":0.518,"repost_share":0.048,"time_to_fill_p50_days":30,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Backend","role_family":"Backend","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":189000,"max_usd":351000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":3667},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-21T00:00:00Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-27T08:25:47Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Job Details:\nJob Description:\nAbout Central Engineering Group\nThe Central Engineering Group (CEG) is Intel's hub for driving innovation and excellence in silicon development. Focused on engineering solutions that power Intel's flagship products, CEG architects, designs, and validates IP foundational to Intel's broader technology portfolio. By joining this team, you will be part of a collaborative, inclusive environment driving advancements to strengthen Intel's leadership in the semiconductor industry.\nPosition Overview\nAs an IP Logic Design Engineer at Intel, you will play a pivotal role in developing high-quality IP blocks and subsystems for integration into full chip designs. You'll be responsible for creating cutting-edge logic designs, optimizing power, performance, and area, and ensuring seamless integration with the broader system. Your contributions will directly impact Intel's ability to deliver next-generation silicon solutions with speed, efficiency, and reliability.\nKey Responsibilities\nDevelop logic designs, register transfer level (RTL) coding, and simulation for IP blocks and subsystems for integration into full chip designs\nDefine architecture and microarchitecture features and ensure their implementation in the design\nOptimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity\nReview verification plans and address RTL test failures to ensure accurate validation of design features\nCollaborate with physical design teams to address floorplan limitations and integrate designs seamlessly\nDrive quality assurance compliance to enable smooth IP-to-SoC handoff\nWhat We're Looking For\nTo be successful in this role, you should demonstrate the following professional traits:\nAbility to collaborate effectively across cross-functional and geographically distributed teams\nStrong attention to detail when reviewing verification plans and resolving design failures\nA passion for innovation and continuous improvement in a fast-paced engineering environment\nQualifications:\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of experience with RTL design and SystemVerilog OR Master's degree in relevant field with 4+ years of experience with RTL design and SystemVerilog\nThe experience must include:\nIndustry-standard tools for front-end design, including synthesis, static timing analysis (STA), and lint checks\nAMBA protocols and coherent protocols such as IDI or CHI\nHardware design concepts such as logic design, state machines, and network-on-chip architectures\nPreferred Qualifications\nExperience with high-speed interconnect designs and power-performance optimization\nProficiency in programming languages such as Python, Perl, or Tcl for scripting automation\nDemonstrated ability to collaborate effectively with cross-functional teams and geographically distributed groups\nWe invite you to bring your expertise and passion to Intel, where you'll work alongside the brightest minds in the industry to develop innovative technologies that redefine the future of computing. Apply now to embark on a rewarding journey and make a lasting impact.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, California, Santa ClaraAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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