{"id":3317029,"url":"https://alion.io/job/intel-platform-signalpower-integrity-engineer-lead","title":"Platform Signal/Power Integrity Engineer Lead","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":91,"ghost_share":0.033,"stale_share":0.505,"repost_share":0.044,"time_to_fill_p50_days":30,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":63000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":true},{"name":"Ansys SIwave","optional":true},{"name":"Cadence Allegro","optional":true},{"name":"Cadence Sigrity","optional":true}],"status":"live","first_seen_at":"2026-10-27T05:44:46Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-29T13:07:32Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Details:\nJob Description:\nJob summaryThe Platform Signal/Power Integrity (SI/PI) Engineer Lead is responsible for defining, developing, and delivering Signal Integrity and Power Integrity solutions for Intel next-generation validation and product platforms. The role provides technical leadership in platform electrical architecture, high-speed interface implementation, schematic design, PCB layout review, routing guideline development, simulation, validation, and debugging activities.\nThe successful candidate will collaborate closely with silicon, package, platform design, PCB layout, firmware, validation, and manufacturing teams to ensure high-performance, robust, and reliable platform designs that meet electrical, timing, signal quality, and power delivery requirements.\nKey Responsibilities:\nLead Signal Integrity and Power Integrity activities for complex platform, board, and package designs.\nPerform pre-layout and post-layout SI/PI simulations and analysis.\nAnalyze and optimize:\nChannel loss\nReflection\nCrosstalk\nJitter\nTiming margin\nPower delivery network (PDN) performance\nPower noise and voltage droop\nDevelop electrical budgets and design margin requirements for high-speed interfaces.\nCorrelate simulation results with laboratory measurements and validation data.\nDrive platform electrical architecture and implementation reviews.\nPerform schematic capture and detailed schematic reviews for complex validation and production platforms.\nReview power architecture, voltage regulator implementation, termination schemes, and interface connectivity.\nDefine stack-up, impedance, return path, and power distribution requirements.\nEnsure compliance with platform electrical specifications and design targets.\nDevelop and maintain PCB design guidelines and routing constraints.\nDefine routing requirements for high-speed interfaces including:\nDDR4/DDR5\nPCIe Gen4/Gen5/Gen6\nUSB4/Thunderbolt\nEthernet\nCXL\nHigh-speed SerDes links\nConduct PCB layout reviews and provide sign-off recommendations.\nDrive implementation reviews for:\nLength matching\nDifferential pair routing\nReference plane transitions\nVia optimization\nReturn path continuity\nDecoupling placement\nEMI-sensitive routing practices\nWork closely with PCB layout engineers and board vendors to resolve implementation issues.\nGenerate and maintain platform SI/PI design guidelines.\nDevelop interface-specific routing recommendations and implementation specifications.\nDocument design rules, characterization reports, simulation methodologies, and lessons learned.\nCreate customer-facing and internal SI/PI collateral supporting platform development and deployment.\nDevelop validation methodologies and compliance testing plans.\nPerform electrical characterization and measurements using:\nOscilloscopes\nVector Network Analyzers (VNA)\nTDR/TDT equipment\nLogic analyzers\nProtocol analyzers\nDebug signal integrity, timing, and power delivery failures.\nLead root-cause analysis and corrective action activities during board bring-up and validation.\nLead SI/PI reviews across multiple platform programs.\nMentor engineers in SI/PI methodology, PCB design practices, and debugging techniques.\nDrive best practices and continuous improvement initiatives.\nProvide technical leadership across platform, silicon, package, and validation organizations.Qualifications:\nMinimum Qualifications\nBachelor's, Master's, or PhD degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n9+ years of experience in Signal Integrity, Power Integrity, Platform Hardware Design, or Board Design.\nStrong understanding of high-speed digital design and power delivery architectures.\nExperience with high-speed PCB design and implementation.\nHands-on experience performing schematic review and board-level electrical analysis.\nKnowledge of transmission line theory, channel modeling, termination techniques, and power distribution network analysis.\nStrong understanding of SI/PI fundamentals, including:\nCrosstalk\nReflection\nJitter\nEye diagram analysis\nS-Parameters\nPower noise\nVoltage droop\nProven debugging and root-cause analysis skills.\nExcellent communication and cross-functional collaboration skills.\nPreferred Qualifications\nSI/PI Tools\nExperience with:\nCadence Sigrity\nCadence Allegro\nAnsys HFSS\nAnsys SIwave\nADS\nSPICE-based simulation tools\nPower-aware SI/PI simulation tools\nPlatform Design Experience\nExperience reviewing and signing off:\nSchematics\nPCB layouts\nRouting constraints\nSI/PI compliance requirements\nExperience defining routing guidelines and electrical design rules for high-speed interfaces.\nFamiliarity with package-board co-design methodologies.\nKnowledge of DFM, DFT, and reliability considerations.\nInterface Expertise\nDemonstrated experience with one or more of:\nDDR4 / DDR5\nLPDDR4 / LPDDR5\nPCIe Gen4 / Gen5 / Gen6\nUSB4 / Thunderbolt\nEthernet\nSATA\nCXL\nUCIe\n• High-speed SerDes technologies\nJob Type:\nExperienced HireShift:\nShift 1 (Malaysia)Primary Location:\nMalaysia, PenangAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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