{"id":2985913,"url":"https://alion.io/job/intel-power-delivery-design-engineer","title":"Power Delivery Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":88,"ghost_share":0.034,"stale_share":0.523,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Operations","role_family":"Operations","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":76000,"max_usd":141000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":261},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys SIwave","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"LTspice","optional":false}],"status":"live","first_seen_at":"2026-10-20T00:00:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T03:51:18Z","board_verified":false,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Job Details:\nJob Description:\nAre you passionate about computing and AI accelerators?\nDo you thrive on innovation and want to disrupt the industry? Are you eager to work with leading AI hardware engineers on Intel's latest architecture? If you love collaborating with diverse teams to create best-in-class AI compute platforms, Intel's GPE department has exciting opportunities for you.\nAs a member of the GPE team, you will develop hardware and platform solutions for Intel products, including the newest IPs targeted at next-generation GPUs and AI accelerators.\nYou will have the opportunity to engage in enabling technologies in PCB design, manufacturing, testing, and debugging. We are a winning team with a clear vision of delivering competitive and cutting-edge products, and we are committed to building the best products and developing the best skills for our team.\nKey Responsibilities:\nWork on end-to-end power delivery design and development, from initial concept to implementation of power delivery requirements and ecosystem enabling power integrated circuits.\nOwn power integrity simulation for the platform power delivery network: build and correlate VRM-to-die PDN models, run DC IR-drop and AC target-impedance analysis, and perform transient droop and Ldi/dt studies across die, package, and PCB to set the decoupling and stack up strategy before layout is committed.\nApply knowledge of power conversion topologies, including components, compensation circuits/stability analysis, drop/droop analysis, simulation tools, and techniques, as well as PCB layout and design tools, to characterize performance and validate correlation of simulation modeling and results.\nDesign and validate platform power conversion and management solutions, including energy management, and perform simulation and optimization for package and PCB, including stack up, power/ground noise plane assignment, decoupling solutions, and/or power sequencing requirements.\nDesign for debug: architect observability into the board from the start, including per-rail voltage and current sense points, Kelvin-sense and probe landing points, telemetry and current-monitor access (SVID/PMBus/IMON), rail-level isolation and enable control, and voltage-margining , so power-on and post-silicon issues can be isolated on the first board instead of a respin.\nDesign for flexibility: build configurability into the power delivery solution so a single board can support multiple SKUs and derivatives, using stuffing options for phase count and decoupling, pin-compatible dual-source regulator footprints, rail split/merge and current headroom for higher-power SKUs, and programmable load line, compensation, and VID range.\nCreate and execute test plans to validate and characterize power delivery solutions.\nCorrelate bench and VR test tool measurements with simulation results to improve simulation model accuracy and close the loop on power integrity assumptions.\nConduct failure analysis and root cause investigations for power delivery issues, implementing corrective actions to prevent recurrence.\nCollaborate with silicon and platform architects to generate solutions and analyses, delivering content into platform design guides as solution collaterals for end customers.\nCollaborate with cross-functional teams, including board design, SW/FW, and systems validation, to ensure seamless integration of power delivery solutions.\nQualifications:\nMinimum Qualifications, you must possess the below minimum qualifications to be initially considered for this position.\nBachelor's or Master's degree in Electrical Engineering or a related field.\n5+ years of experience in:\nDesigning low voltage, high current, multi-phase DC-DC switching regulators (buck, boost, etc.) to meet stringent targets, optimizing the design for transient response and conversion efficiency.\nWorking with signal/power integrity and power delivery network simulation tools such as Cadence Sigrity PowerDC/PowerSI, Ansys SIwave etc. to develop accurate models of circuit design \nDesign and optimize accurate power delivery simulation models using SPICE and time-based simulation tools (LTSpice, SIMPLIS etc.) based on SOC design power requirements.\nPower delivery network modeling across die, package, and PCB, including stackup, plane assignment, decoupling network design, and S-parameter extraction and correlation.\nExperience using oscilloscopes and DAQ for hardware troubleshooting and debugging.\nInteracting with Signal Integrity, Layout, and Mechanical engineers, with working knowledge of SI/PI, PCB layout, and mechanical aspects of board designs.\n\nPreferred Qualifications, are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nExperience designing for debug and testability on power delivery hardware, including sense and telemetry instrumentation, voltage margining, and rail isolation for post-silicon bring-up.\nExperience designing configurable power delivery solutions that support multiple SKUs and derivative products from a single board design.\nIdentify new technologies/interfaces and develop board power delivery architecture.\nExperience in project management, including leading projects and manage timelines and resources effectively.\nFamiliarity with emerging technologies such as GaN power devices, switched capacitor topology, etc.\nExperience delivering products for high-volume production and cost optimization.\nKnowledge of board and power management (HW/SW/FW) debugging.\nWilling to provide hardware technical support to ODM/OEM board vendors.\nWillingness to travel globally to meet internal teams and external customers.\nJob Type:\nExperienced HireShift:\nShift 1 (Canada)Primary Location:\nCanada, TorontoAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AAnnual Salary Range for jobs which could be performed in Canada\nSalary range dependent on a number of factors including location and experience.\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.Canada Accommodation:\nIntel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.\n*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":7154,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T08:25:14Z"}],"visa":[],"liveness":{"score":57,"band":"ok","label":"Likely open","p_open":0.9,"p_active":0.632,"p_room":1,"age_days":6,"expected_fill_days":30,"reasons":["conf:50","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/intel-power-delivery-design-engineer","json_url":"https://alion.io/job/intel-power-delivery-design-engineer.json","meta":{"generated_at":"2026-10-26T19:02:58Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":25641,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-power-delivery-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-power-delivery-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-power-delivery-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-power-delivery-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-power-delivery-design-engineer"}]}