{"id":2986023,"url":"https://alion.io/job/intel-senior-cad-engineer-floor-plan","title":"Senior CAD Engineer - Floor Plan","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":90,"ghost_share":0.033,"stale_share":0.533,"repost_share":0.044,"time_to_fill_p50_days":30,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false}],"status":"live","first_seen_at":"2026-10-15T00:00:00Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-27T19:23:25Z","board_verified":true,"closed_at":null,"days_open":13,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":13},"description":"Job Details:\nJob Description:\nWe are seeking a highly motivated Senior CAD Engineer for CPU IP Design Planning Methodology and Automation to support, maintain, enhance, and deploy Design Planning and RTL to Floorplan methodologies for next generation CPU IP development.The successful candidate will work closely with CPU Physical Design, Architecture, RTL, and CAD teams to enable efficient and scalable Design Planning workflows. This role focuses on methodology development, flow support, automation, infrastructure maintenance, and productivity improvements across multiple CPU programs.\nThe ideal candidate combines a strong understanding of Physical Design and Design Planning concepts with expertise in CAD methodologies, EDA tools, scripting, and software development.\nKey Responsibilities\n-Own and support Design Planning and RTL to Floorplan methodology deployment across CPU IP programs.\n-Develop, maintain, and enhance automation frameworks supporting RTL to Floorplan, Design Planning, physical aware RTL analysis, floorplan generation flows, PPA estimation methodologies, and early congestion and routability analysis.\n-Provide technical support to Physical Design teams by debugging flow, tool, and methodology issues.\n-Drive continuous improvements in Design Planning flow quality, robustness, scalability, and usability.\n-Develop automation solutions to improve engineering productivity and reduce manual effort.\n-Create dashboards, reporting infrastructure, and analytics frameworks to track methodology health, usage, and quality metrics.\n-Work closely with implementation teams to identify workflow bottlenecks and deploy automation based solutions.\n-Support the adoption and deployment of new EDA tool capabilities, releases, and methodology enhancements.\n-Enable methodology correlation and consistency across CPU IP projects and technology nodes.\n-Partner with internal CAD organizations and EDA vendors to evaluate and integrate new Design Planning capabilities.\n-Drive best practices, documentation, training materials, and user support for Design Planning methodologies.\n-Explore Machine Learning, Generative AI, and Agentic AI solutions to improve methodology deployment, flow debugging, and productivity.\nQualifications:\nMinimum QualificationsM.Tech/MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related field.\n4+ years of industry experience in:\nCAD Engineering\nDesign Automation\nPhysical Design Methodology\nEDA Tool Development\nPhysical Design Infrastructure\nStrong understanding of:\nPhysical Design flows\nRTL-to-Floorplan methodologies\nDesign Planning concepts\nFloorplanning fundamentals\nPPA analysis and optimization\nExperience supporting and deploying implementation tools such as:\nSynopsys Fusion Compiler\nICC2\nCadence Innovus\nEquivalent physical implementation platforms\nStrong software development and scripting skills in:\nPython\nTcl\nShell Scripting\nExperience building and maintaining production-quality CAD automation and methodology frameworks.\nPreferred Qualifications\nExperience supporting CPU Core, Cache, Fabric, or other high-performance IP development teams.\nExperience developing methodologies and automation for:\nRTL-FP\nDesign Planning\nPhysical-aware design\nDesign quality assessment\nEarly PPA estimation\nExperience with advanced technology nodes such as Intel 18A/14A, TSMC N3/N2, or equivalent.\nExperience with distributed compute infrastructure, cloud-based design environments, and large-scale CAD systems.\nFamiliarity with Machine Learning, Data Analytics, LLMs, and Agentic AI frameworks for EDA applications.\n• Working knowledge of timing, power, congestion, routability, and signoff considerations impacting design planning methodologies.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":5004,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T08:25:14Z"}],"visa":[],"liveness":{"score":56,"band":"ok","label":"Likely open","p_open":1,"p_active":0.619,"p_room":0.9,"age_days":13,"expected_fill_days":30,"reasons":["conf:10","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-28T05:59:10Z"},"pay":null,"html_url":"https://alion.io/job/intel-senior-cad-engineer-floor-plan","json_url":"https://alion.io/job/intel-senior-cad-engineer-floor-plan.json","meta":{"generated_at":"2026-10-28T06:20:22Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8301,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-senior-cad-engineer-floor-plan"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-senior-cad-engineer-floor-plan"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-senior-cad-engineer-floor-plan"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-senior-cad-engineer-floor-plan\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-senior-cad-engineer-floor-plan"}]}