{"id":2986026,"url":"https://alion.io/job/intel-senior-cad-engineer-physical-design-signoff","title":"Senior CAD Engineer – Physical Design Signoff","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":104,"ghost_share":0.029,"stale_share":0.538,"repost_share":0.038,"time_to_fill_p50_days":30,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"AI Agents","optional":true}],"status":"live","first_seen_at":"2026-10-15T00:00:00Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-11-11T17:24:48Z","board_verified":true,"closed_at":null,"days_open":27,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":27},"description":"Job Details:\nJob Description:\nWe are looking for a highly motivated Senior Physical Design Signoff Automation Engineer to develop and deploy signoff methodologies and automation solutions for advanced CPU and SoC designs. The candidate will work closely with Physical Design, Timing, Power, Reliability, and CAD teams to improve signoff quality, productivity, and turnaround time.The ideal candidate possesses deep expertise in Parasitic Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC), and Power Integrity signoff, along with strong programming and automation skills.\nKey Responsibilities\nDevelop and enhance automation solutions for Physical Design signoff flows, including:\nRC Extraction\nStatic Timing Analysis (STA)\nElectrical Rule Checking (ERC)\nPower Integrity (IR Drop/EM)\nSignal Integrity (SI)\nCreate scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity.\nDevelop scripts and tools to automate signoff checks, debugging, reporting, and data analysis.\nAnalyze and resolve timing, extraction, ERC, and power signoff issues in collaboration with design teams.\nDrive methodology improvements to improve signoff convergence, quality, and correlation across implementation stages.\nPartner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities.\nBuild dashboards and reporting infrastructure to monitor signoff health and project readiness.\nQualifications:\nMinimum QualificationsM.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field.\n8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation.\nStrong proficiency in:\nPython\nTcl\nShell scripting\nPreferred Qualifications\nExperience working on advanced process technologies (3nm, 2nm, Intel 18A/14A, or equivalent).\nUnderstanding of AOCV/POCV and variation-aware timing methodologies.\nFamiliarity with power delivery networks, EM analysis, and reliability signoff.\nExperience in Machine-learning methods and Agentic AI systems to solve CAD problems\nExposure to CPU core, high-performance compute, or large SoC designs.\nExperience with distributed computing environments and large-scale signoff infrastructure.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":3497,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T08:25:14Z"}],"visa":[],"liveness":{"score":45,"band":"ok","label":"Likely open","p_open":1,"p_active":0.599,"p_room":0.75,"age_days":27,"expected_fill_days":30,"reasons":["conf:10","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-11-11T05:49:22Z"},"pay":null,"html_url":"https://alion.io/job/intel-senior-cad-engineer-physical-design-signoff","json_url":"https://alion.io/job/intel-senior-cad-engineer-physical-design-signoff.json","meta":{"generated_at":"2026-11-11T20:12:28Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":39472,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-senior-cad-engineer-physical-design-signoff"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-senior-cad-engineer-physical-design-signoff"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-senior-cad-engineer-physical-design-signoff"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-senior-cad-engineer-physical-design-signoff\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-senior-cad-engineer-physical-design-signoff"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2986026}},{"tool":"search_jobs","arguments":{"company":"intel.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2986026},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}