{"id":4216190,"url":"https://alion.io/job/intel-senior-design-verification-engineer-3","title":"Senior Design Verification Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":111,"ghost_share":0.027,"stale_share":0.586,"repost_share":0.036,"time_to_fill_p50_days":30,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Santa Clara, United States","Phoenix, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"InfiniBand","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-10T00:00:00Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-13T02:48:15Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nAbout the Role\nAs an IP Design Verification Engineer, you will play a critical role in shaping Intel's innovations by ensuring the functionality and reliability of our intellectual property (IP) designs. You will join a dynamic team that collaborates across architecture, design, and verification groups to ensure our solutions meet and exceed industry standards.\nYour work will directly impact the development of groundbreaking technologies, driving Intel's success in delivering world-class products to the market. This is an exciting opportunity to contribute to cutting-edge projects while advancing your career in a forward-thinking and collaborative environment.\nKey Responsibilities\nDevelop and execute comprehensive verification plans to ensure IP logic meets microarchitecture specifications\nCreate and maintain test benches and verification environments to achieve high coverage and reliability\nPerform system simulations to verify designs, analyze power and timing, and identify bugs in the presilicon environment\nDebug verification issues by replicating, root-causing, and implementing corrective measures for failing tests\nCollaborate with architects, RTL developers, and physical design teams to enhance verification methodologies for complex features\nDocument verification plans and drive technical reviews with architecture and design teams\nMaintain and improve existing verification infrastructure, tools, and methodologies\nParticipate in defining verification infrastructure and contribute to the development of technical flow methodologies (TFMs)\nYou Should Demonstrate the Following to Be Successful\nStrong collaboration and communication skills to effectively work across architecture, design, and physical teams\nDemonstrated ability to lead technical reviews and drive alignment on verification strategies\nPassion for continuous learning, innovation, and contributing to a culture of technical excellence\nProven ability to analyze and resolve complex design issues in a presilicon environment\nQualifications:\nMinimum Qualifications\nBachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field\n9+ years of experience in IP functional verification with a Bachelor's degree, 6 years with a Master's degree, or 4 years with a PhD\nThe above experience must include:\nHands-on experience in building verification environments using SystemVerilog and UVM\nExpertise in RTL design and debugging using industry-standard tools and methodologies\nHands-on experience verifying networking IPs/SoCs implementing RDMA (RoCEv2, iWARP, InfiniBand) or comparable reliable transport protocols (e.g., Ultra Ethernet Transport, TCP offload), including features such as QP/connection state, retransmission, packet ordering, and congestion control\nPreferred Qualifications\nFamiliarity with scripting languages, such as Python or Perl, to automate verification tasks\nWe invite you to bring your expertise, creativity, and enthusiasm to Intel. Take the next step in your career by applying today and be part of a team that is shaping the future of technology.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Texas, AustinAdditional Locations:\nUS, Arizona, Phoenix, US, California, Santa ClaraPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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