{"id":4216170,"url":"https://alion.io/job/intel-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":111,"ghost_share":0.027,"stale_share":0.586,"repost_share":0.036,"time_to_fill_p50_days":30,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Hillsboro, United States","Folsom, United States","Austin, United States","Phoenix, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-11T00:00:00Z","employer_posted_date":"2026-11-11","last_verified_at":"2026-11-13T02:48:15Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Details:\nJob Description:\nAbout the Team\nIntel is building something new. The Unified Intel Chassis (UIC) team is a new IP development team focused on chassis and interconnect technology and a configurable generator for SoCs and chiplets. As a Senior Design Verification Engineer, you will verify coherent, non-coherent, and I/O-coherent systems - including interactions among interconnects, caches, memory subsystems, and chassis functions such as clocking, power management, reset, debug, and trace.\nThis is a hands-on technical role spanning the full verification lifecycle: from clarifying requirements and building models and checkers through debugging and verification signoff. You will work closely with engineers across architecture, design, verification, and tooling to turn specifications into working, tested hardware. Simulation, formal verification, and AI-assisted development are part of how we work.\nKey Responsibilities\nOwn verification plans for chassis and interconnect IP, prioritize functional and integration risks, and drive assigned features from initial bring-up through signoff\nBuild reusable environments, reference models, and checkers for data integrity, ordering, address translation, access permissions, interrupt routing and delivery, and forward progress under concurrent traffic and backpressure\nCombine simulation, formal properties, and targeted experiments to find bugs; review assumptions, checker completeness, coverage gaps, and proof results rather than relying on passing regressions alone\nCollaborate with design and verification engineers to define interface contracts, share VIP and assertions, and debug interactions across data paths, clock and power transitions, reset sequences, and debug and trace functions\nWork with architecture, design, and tooling engineers to clarify specifications, evaluate tradeoffs, and contribute reviewed changes to models, RTL, and verification infrastructure\nDevelop configuration-driven regressions and AI-assisted workflows for coding, property development, and debug; validate generated work with independent checks and reproducible tests across supported configurations\nMentor engineers through code and testplan reviews, communicate remaining risks, and establish clear evidence for verification closure\nWhat We're Looking For\nYou should demonstrate the following professional traits to be successful:\nDemonstrated ownership of complex verification work through closure, including cross-block root-cause analysis and clear technical communication across engineering disciplines\nA collaborative approach to working across architecture, design, and verification teams to define requirements, resolve ambiguity, and drive toward shared goals\nA rigorous, evidence-driven mindset - one that questions assumptions, validates generated work independently, and communicates risk clearly rather than relying on surface-level indicators of completeness\nQualifications:\nMinimum Qualifications\nBS/MS in Electrical Engineering, Computer Science, or related field with 10+ years of relevant experience in design verification; background in IP DV with significant experience in subsystem and SoC-level verification\nThe experience must include:\nHands-on experience verifying high-performance interconnects and memory subsystems, with an understanding of coherent, non-coherent, and I/O-coherent operation, cache coherency, memory consistency, transaction ordering, virtual memory, I/O Memory management units (IOMMUs), and interrupt controllers; experience with MESI/MOESI-based coherency mechanisms and protocols such as AMBA CHI, CXL, or comparable architectures\nSystemVerilog/UVM and assertion-based verification skills, with practical experience applying formal verification alongside simulation and understanding the limits of each method\nProgramming and debugging skills in SystemVerilog and Python or C/C++; ability to read RTL, build independent reference models and checkers, and develop maintainable test automation\nPreferred Qualifications\nExperience with configurable interconnect generators, generated testbenches, and verification across topology, parameter, and multi-die configurations\nExperience with formal abstraction and proof decomposition, or emulation-based validation of system workloads\nExperience verifying clocking, power management, reset, debug, trace, RAS, security isolation, or QoS interactions at subsystem level\nKnowledge of cache hierarchies, home nodes, duplicate-tag structures, snoop filters, memory controllers, and how their interactions affect correctness and performance\nExperience building and evaluating AI-assisted engineering workflows, including checks for incorrect generated code, properties, or specification interpretations\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, California, Santa ClaraAdditional Locations:\nUS, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Texas, AustinPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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