{"id":3531363,"url":"https://alion.io/job/intel-senior-pdk-physical-verification-engineer","title":"Senior PDK Physical Verification Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":96,"ghost_share":0.031,"stale_share":0.49,"repost_share":0.042,"time_to_fill_p50_days":30,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States","Santa Clara, United States","Austin, United States","Phoenix, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":153000,"max_usd":282000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Pegasus","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Cadence Virtuoso","optional":true},{"name":"Linux","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2026-10-28T00:00:00Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-10-31T12:58:18Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Details:\nJob Description:\nShape the Future of Advanced Semiconductor Technology at Intel\nJoin Intel's Design Technology Platform (DTP) organization and become part of a world-class team enabling the next generation of semiconductor innovation. In this highly visible role, you will develop and deploy advanced density fill methodologies and Process Design Kit (PDK) solutions that directly impact Intel's most advanced technology nodes and product designs.\nWorking at the intersection of process technology, physical verification, and design automation, you will collaborate with leading engineers across Intel and the EDA ecosystem to solve complex manufacturability challenges, improve design productivity, and enable breakthrough technologies. Your contributions will influence how future products are designed and manufactured, helping Intel maintain technology leadership in an increasingly competitive industry.\nWhat You'll Do\nLead the development, implementation, and validation of density fill solutions within advanced Process Design Kits (PDKs).\nDevelop algorithmic solutions using industry-leading physical verification platforms, including Calibre, Synopsys ICV, and Cadence Pegasus, to ensure density compliance and manufacturability across advanced process technologies.\nCollaborate with process integration teams, design rule owners, product design engineers, and customers to define requirements and deliver state-of-the-art solutions.\nDrive automation initiatives that improve engineering efficiency, solution scalability, and deployment across multiple design environments.\nDesign and develop robust validation frameworks, test suites, and qualification methodologies to ensure high-quality tool and rule deck releases.\nAdvance innovative physical verification methodologies to address emerging challenges associated with technology scaling.\nPartner closely with external EDA vendors to influence and deploy next-generation tool capabilities and methodologies.\nDevelop technical documentation, training materials, and best practices that enable successful adoption across Intel's design community.\nServe as a technical expert and contribute to strategic initiatives that shape Intel's design enablement roadmap.\nIdeal Candidate Background\nWe are particularly interested in candidates who have developed physical verification methodologies, density-fill solutions, or PDK technologies within:\nSemiconductor Foundries.\nIntegrated Device Manufacturers (IDMs).\nAdvanced Packaging and OSAT Organizations.\nEDA Software Companies.\nDesign Enablement or CAD Teams supporting advanced-node development.\nCore Competencies\nExcellent communication and technical presentation skills, with the ability to translate complex technical concepts into actionable solutions.\nStrong problem-solving, debugging, and analytical skills.\nStrong understanding of technology scaling challenges and their impact on physical verification and design rule development.\nQualifications:\nThe Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 6+ years of relevant experience;OR - Master's degree with 5+ years of experience.\nOR - PhD with 2+ years of experience.\n\n4+ years of hands-on experience with at least one industry-standard physical verification platform such as Calibre, ICV, or Pegasus, including methodology development, rule deck debugging, validation, or production deployment.\n3+ years of experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, PVL, or Tcl-based verification environments.\nExperience with semiconductor process technology, device physics, design rules, and manufacturability requirements.\nExperience developing algorithmic solutions for physical design and manufacturing challenges at advanced technology nodes.\nExperience with with Unix/Linux operating systems and engineering computing environments.\nPreferred Qualifications\n4+ years of direct experience developing, deploying, or supporting density fill methodologies for advanced semiconductor technologies at 16nm and below.\nProven expertise in fill rule implementation, density optimization, and manufacturing-driven design methodologies.\nDeep experience with physical verification flows, including DRC, density analysis, fill verification, and process-aware design enablement.\nExperience supporting or developing solutions for leading foundry, IDM, or advanced process technologies.\nFamiliarity with custom layout environments such as Cadence Virtuoso or Synopsys Custom Designer.\nExperience collaborating across multidisciplinary engineering teams and external partners to deliver innovative solutions.\nExperience leading technical initiatives, driving process improvements, or influencing product and methodology roadmaps.\nPrior experience with semiconductor foundries, IDMs, OSATs, or EDA vendors developing physical verification methodologies, density-fill solutions, PDKs, or design-for-manufacturing technologies is highly desirable.\nWhy Intel?\nThis role offers a rare opportunity to work on technology challenges that influence the future of semiconductor manufacturing. You'll collaborate with experts across process technology, CAD, physical design, and EDA while helping define methodologies used across Intel's most advanced products. If you are passionate about solving complex physical verification and manufacturability problems at scale, this role offers both significant technical depth and broad organizational impact. Join Intel and make a direct impact on the next generation of semiconductor innovation.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nUS, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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