{"id":3935770,"url":"https://alion.io/job/intel-senior-principal-engineer-device-design","title":"Senior Principal Engineer, Device Design","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":103,"ghost_share":0.029,"stale_share":0.553,"repost_share":0.058,"time_to_fill_p50_days":30,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hillsboro, United States","Santa Clara, United States","Phoenix, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Design of Experiments","optional":false},{"name":"Statistical Process Control","optional":true}],"status":"live","first_seen_at":"2026-11-06T00:00:00Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-08T12:06:11Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Details:\nJob Description:\nAbout the Group\nIntel is transforming from an Integrated Device Manufacturer (IDM) to a leading global foundry service provider, offering world-class manufacturing capabilities to external customers worldwide. Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation-focusing on technology customization, yield improvement, performance optimization, and exceptional customer delivery.\nAbout the Role\nWe are seeking a highly accomplished Senior Principal Device Design Engineer with broad semiconductor industry expertise to drive the high-level architecture, definition, and optimization of next-generation and high-volume manufacturing (HVM) semiconductor technologies. In this strategic technical leadership role, you will apply a deep mastery of semiconductor device physics to define technical roadmaps and ensure world-class performance across a diverse range of applications-including advanced logic, SRAM, low-power mobile, analog, and mixed-signal designs.\nServing as a primary technical bridge between Process Integration, Yield, and Module Engineering, and collaborative product partners, you will establish the technical direction, target validations, and silicon-to-simulation accuracy across Intel's diverse technology portfolio.\nKey Responsibilities:\nTechnical Strategy and Architecture Leadership: Lead cross-functional, multi-disciplinary teams in defining base and derivative semiconductor architectures-including advanced transistors, interconnects, and design rules-tailored for high-performance logic, low-power, memory, analog, and mixed-signal applications.\nTechnical Partner and Customer Engagement: Partner directly with external customers, product design teams, and internal engineering groups to understand complex product requirements, resolve circuit-level performance/reliability/leakage trade-offs, and translate product needs into tailored silicon solutions.\nTechnology Customization and Optimization: Drive the development and implementation of customized semiconductor features across logic and memory technologies, ensuring seamless integration with existing manufacturing processes and platforms to support specialized applications.\nSilicon-to-Simulation Readiness: Set and govern device and interconnect performance targets, evaluating silicon-to-simulation health, model readiness, and design feasibility for large-volume manufacturing.\nCross-Functional Integration: Serve as the authoritative technical interface bridging Process Integration, Process Module, Device Physics, Yield Engineering, and Product Design to coordinate complex technology handoffs and resolve system-level constraints.\nDesign Rule and Waiver Governance: Direct the validation and strategic waiver management processes for advanced design rules, balancing strict manufacturing compliance and yield with product design flexibility.\nAdvanced Data Analytics: Guide the evaluation of electrical test (E-test) and yield data using advanced statistical methods and data analysis techniques to translate experimental silicon data into actionable process and design intelligence.\nMentorship and Industry Thought Leadership: Provide senior technical mentorship to engineers and researchers across the organization, stay ahead of emerging semiconductor industry trends, and foster a culture of technical excellence and customer-centric innovation.\nRequired Skills and Experience:\nProgressive experience in the semiconductor industry with a strong focus on CMOS device physics, device design, and semiconductor technology development.\nLeadership and Technology Integration: Demonstrated technical leadership within the semiconductor industry, specifically leading cross-functional teams to define, develop, and deliver advanced semiconductor technologies (covering logic, memory, or integrated architectures) and design rules into High-Volume Manufacturing (HVM).\nDesign Rule Governance: Deep proficiency in design rule development, validation, and waiver management processes, with a strong understanding of how layout constraints impact product yield.\nData and Analytical Mastery: Proven expertise in statistical data analysis, Design of Experiments (DOE), and data interpretation to evaluate test chip, E-test, and yield trends.\nPreferred Skills and Experience\nAdvanced and Specialty Node Expertise: Architectural experience in advanced-node transistor design and scaling, with deep experience in specialized semiconductor customization for low-power, analog, mixed-signal, and memory technologies.\nPhysical Verification and Mask Flows: High-level familiarity with physical verification flows, Design Rule Checker (DRC) development, and mask generation concepts.\nManufacturing and SPC: Extensive experience in a High-Volume Manufacturing (HVM) environment with a focus on statistical process control (SPC) and yield monitoring.\nExecutive Communication: Exceptional verbal and written communication skills, with a demonstrated ability to influence executive stakeholders and guide collaborative partners through complex technical trade-offs.\nQualifications:\nMaster's degree in Electrical Engineering, Physics, Material Science, or a related field. PhD preferred\n15+ years of relevant semiconductor device and technology development experience.\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Oregon, HillsboroAdditional Locations:\nUS, Arizona, Phoenix, US, California, Santa ClaraPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $265,480.00-374,800.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":7858,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-08T07:30:44Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 2,029 · green card filings: 490","filings_12m":2029,"filings_prev_12m":3014,"green_card_filings_12m":490,"median_offered_wage_usd":134832,"route":null,"cap_exempt":false,"checked_at":"2026-11-08T10:45:15+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":2,"expected_fill_days":30,"reasons":["conf:0","win:early","comp:brand"],"computed_at":"2026-11-08T12:28:01Z"},"pay":null,"html_url":"https://alion.io/job/intel-senior-principal-engineer-device-design","json_url":"https://alion.io/job/intel-senior-principal-engineer-device-design.json","meta":{"generated_at":"2026-11-08T12:28:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":26530,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-09T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-senior-principal-engineer-device-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-senior-principal-engineer-device-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-senior-principal-engineer-device-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-senior-principal-engineer-device-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-senior-principal-engineer-device-design"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3935770}},{"tool":"search_jobs","arguments":{"company":"intel.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3935770},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}