{"id":2986025,"url":"https://alion.io/job/intel-senior-technical-lead-cpu-physical-design","title":"Senior Technical Lead - CPU Physical Design","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":92,"ghost_share":0.033,"stale_share":0.5,"repost_share":0.043,"time_to_fill_p50_days":30,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":79000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":14,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false},{"name":"AI Agents","optional":true},{"name":"Machine Learning","optional":true}],"status":"live","first_seen_at":"2026-10-15T00:00:00Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-30T01:07:41Z","board_verified":true,"closed_at":null,"days_open":15,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":15},"description":"Job Details:\nJob Description:\nWe are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The successful candidate will provide technical leadership across the physical design lifecycle, driving PPA optimization, execution excellence, methodology adoption, and design convergence for high-performance CPU products.The ideal candidate brings deep expertise in advanced-node physical design, strong technical leadership, and a proven track record of delivering complex CPU, SoC, or high-performance IP designs.\nKey Responsibilities\nLead physical design execution for CPU IPs from design planning through signoff.\nProvide technical leadership for:\nFloorplanning and Design Planning\nPlacement and Optimization\nClock Tree Synthesis\nRouting and Physical Verification\nTiming Closure\nPower and Area Optimization\nSignoff Readiness\nDrive PPA convergence and deliver aggressive frequency, power, and area targets.\nDefine and execute physical design strategies for advanced CPU architectures and technology nodes.\nPartner closely with Architecture, RTL, Circuit Design, DFT, CAD, Power, and Signoff teams to drive implementation success.\nLead resolution of complex implementation, timing, congestion, and power challenges.\nDrive methodology improvements and adoption of best practices across multiple projects.\nEvaluate implementation tradeoffs and provide technical recommendations that influence architecture and design decisions.\nMentor and guide engineers across the physical design organization.\nCollaborate with CAD teams to improve efficiency through automation, methodology enhancements, and AI-driven workflows.\nSupport planning, estimation, risk assessment, and execution tracking for physical design deliverables.\nContribute to hiring, technical interviews, and development of engineering talent.\nQualifications:\nMinimum QualificationsM.Tech/MS/PhD in Electrical Engineering, Computer Engineering, VLSI, or a related discipline.\n14+ years of industry experience in ASIC or CPU Physical Design.\nProven experience delivering successful products through complete physical implementation and signoff cycles.\nStrong expertise in:\nFloorplanning and Design Planning\nPlacement and Optimization\nClock Tree Synthesis\nRouting and Closure\nStatic Timing Analysis\nSignal Integrity\nPower Integrity and EM/IR\nPhysical Verification\nHands-on experience with industry-standard implementation tools such as:\nSynopsys Fusion Compiler\nICC2\nCadence Innovus\nPrimeTime\nStarRC\nRedHawk\nCalibre\nStrong scripting and automation experience using:\nPython\nTcl\nShell\nPreferred Qualifications\nExperience delivering high-performance CPU core, cache, fabric, or compute IP designs.\nExperience with advanced process technologies such as Intel 18A/14A, TSMC N3/N2, or equivalent.\nDeep understanding of:\nPhysical design methodologies\nAdvanced timing closure techniques\nHierarchical implementation\nVariation-aware design methodologies\nPower-aware implementation\nExperience leading geographically distributed teams.\nExperience driving CAD methodology improvements and automation initiatives.\nFamiliarity with AI, Machine Learning, and Agentic AI applications for design automation and productivity enhancement.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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