{"id":2985931,"url":"https://alion.io/job/intel-signal-integrity-student-worker-engineer","title":"Signal Integrity Student Worker Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":88,"ghost_share":0.034,"stale_share":0.523,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"part_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Heredia, Costa Rica"],"countries":["CR"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":41000,"max_usd":100000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":769},"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Physical AI","optional":false},{"name":"Ansys HFSS","optional":true},{"name":"Ansys SIwave","optional":true},{"name":"Cadence Sigrity","optional":true},{"name":"JMP","optional":true},{"name":"MATLAB","optional":true},{"name":"Synopsys HSPICE","optional":true}],"status":"live","first_seen_at":"2026-10-20T00:00:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T03:51:18Z","board_verified":false,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Job Details:\nJob Description:\nAs a Physical Design Engineering Undergraduate Intern, you will contribute to the physical implementation of platform designs to ensure readiness for manufacturing. For this role the candidate would support Signal Integrity engineers in electrical design and validation activities for Client, Edge and Physical AI platforms, you will be working on design, deploy, and optimize high-speed interconnect architecture. This role offers hands-on experience in physical design flows, enabling you to build skills, apply knowledge, and explore future career opportunities.\nThe Silicon and Platform Engineering Group (SPE) drives innovation and ensures the physical designs of silicon and platforms meet manufacturing and performance standards. The team focuses on delivering scalable, efficient solutions that support Intel's broader goals of advancing technology and enabling cutting-edge products. Joining this group means becoming part of a collaborative environment dedicated to excellence in engineering and design.\nThe primary responsibilities for this role will include, but are not limited to:\nAssist in the physical implementation of package and platform designs, contributing to the Signal Integrity of the High Speed Interconnects.\nCollaborate with cross-functional teams to support design scalability, automation, and manufacturability.\nEngage in verification and signoff activities to ensure compliance with performance and manufacturing standards.\nApply theoretical knowledge to practical projects, gaining exposure to physical design optimization, signal integrity analysis, and noise glitch evaluation.\nSupport design initiatives aligned with Intel's business goals, leveraging advanced tools and methodologies.\nQualifications:\nMinimum Qualifications:\nMinimum qualifications are required to be initially considered for this position.\nPursuing a Bachelor's degree in Electronics or Electrical Engineering with at least 50 percent of courses completed, or pursuing a Master's degree in the same field.\nBachelor's candidates must demonstrate 0-1 years of hands-on experience in physical design, with skills gained through internships, academic projects, coursework, or hands-on training. Master's candidates require no prior professional experience.\nProficiency in English (written and verbal).\nCompletion of at least 1-2 courses in Electrical/Electromagnetic fundamentals.\nMaintain a minimum of 80 percent GPA.\nAvailability to work at least 22.5 hours per week during the internship period.\nDisposition to work a minimum of 1 year in this position.\nMust have unrestricted - permanent right to work in Costa Rica.\nPreferred Qualifications:\nPreferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nKnowledge of electrical simulation tools such as Sigrity PowerSI, SiWave, Hspice, Matlab, or Ansys HFSS.\nFamiliarity with PCB design and circuit simulators.\nExperience using statistical analysis tools such as JMP.\nStrong communication skills with an eagerness to learn and solve technical challenges collaboratively.\nJoin us in shaping the future of technology through innovation, collaboration, and your unique contributions-apply today to make an impact with Intel.\nJob Type:\nStudent / InternShift:\nShift 1 (Costa Rica)Primary Location:\nCosta Rica, San JoseAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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