{"id":3753125,"url":"https://alion.io/job/intel-silicon-domain-architect","title":"Silicon Domain Architect","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":103,"ghost_share":0.029,"stale_share":0.553,"repost_share":0.058,"time_to_fill_p50_days":30,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"Grafana","optional":true},{"name":"Plotly","optional":true},{"name":"Power BI","optional":true},{"name":"Tableau","optional":true}],"status":"live","first_seen_at":"2026-11-03T00:00:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-07T03:00:07Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Details:\nJob Description:\nAbout the Role and TeamThe AI Silicon Architecture and Performance Engineering team is responsible for developing and maintaining performance models that enable architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. These models are a critical component of the product development process, providing early visibility into architectural tradeoffs, bottlenecks, and optimization opportunities long before silicon availability.\nWe are seeking a highly experienced and motivated engineer to drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement activities. The candidate will work closely with architects, performance stimulus generation teams, silicon design teams, and product stakeholders to evaluate and optimize key AI silicon subsystems that determine overall platform scalability and performance.\nThe role focuses on performance modeling and analysis of AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure. The successful candidate will leverage SystemC/TLM-based modeling methodologies to generate actionable insights that directly influence architecture and product decisions.\nThis position requires a unique combination of software development expertise, architecture understanding, analytical problem solving, and cross-functional technical leadership. The engineer will be expected to independently drive complex technical initiatives while serving as a trusted performance expert across multiple organizations.\n________________________________________\nKey Responsibilities\n1. AI Silicon Performance Model Development\nDevelop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems.\nDrive modeling of key architectural components including:\no SoC fabrics and on-chip communication networks\no Memory controllers and memory subsystem behavior\no Scale-up controllers and fabrics enabling accelerator-to-accelerator communication within a node, tray, or pod\no Scale-out controllers and fabrics enabling communication across nodes, racks, and larger AI clusters\no Host CPU to accelerator memory paths\no Local, host, and remote memory access paths\no End-to-end data movement architectures\nImplement new architectural features and capabilities based on evolving product requirements.\nImprove model fidelity, scalability, maintainability, and simulation performance.\nPerform detailed debugging and root-cause analysis of model issues and performance anomalies.\nContribute to the evolution of modeling infrastructure, methodologies, and best practices.\n________________________________________\n2. Functional Validation and Model Correlation\nDefine and execute comprehensive validation strategies to ensure correctness and architectural accuracy of performance models.\nDevelop validation plans, regression suites, coverage methodologies, and quality metrics.\nCorrelate modeled behavior against architectural expectations, reference simulations, performance projections, and available hardware measurements.\nInvestigate and resolve discrepancies between expected and observed behavior.\nEstablish robust validation frameworks that improve stakeholder confidence in model-generated performance projections.\nContinuously improve validation methodologies and model quality.\n________________________________________\n3. AI Silicon Performance Characterization and Architectural Analysis\nDesign and execute performance studies covering a wide range of workloads, traffic patterns, and system configurations.\nAnalyze performance of communication fabrics, memory systems, and data movement paths under representative AI workloads.\nEvaluate bandwidth utilization, latency characteristics, congestion behavior, traffic distribution, buffering efficiency, and resource utilization.\nCharacterize interactions across local memory, host memory, and remote memory domains.\nAssess scalability of scale-up and scale-out architectures across increasingly larger deployment footprints.\nIdentify performance bottlenecks and quantify their impact on overall system throughput and efficiency.\nConduct architectural tradeoff studies to evaluate alternative design approaches.\nProvide performance-driven recommendations that influence architecture and product decisions.\n________________________________________\n4. Performance Data Generation, Analytics and Visualization\nDevelop frameworks and methodologies for large-scale performance data generation and analysis.\nCreate automated workflows for data collection, processing, correlation, and reporting.\nDevelop performance dashboards and visualization tools that simplify interpretation of complex performance data.\nDefine and track meaningful performance KPIs and architectural metrics.\nUtilize Python-based analysis frameworks to process large datasets and generate actionable insights.\nEnable efficient consumption of performance information by architects, designers, and engineering leadership.\n________________________________________\n5. Cross-Functional Technical Leadership and Stakeholder Engagement\nPartner closely with architecture teams, performance stimulus generation teams, silicon design teams, and product stakeholders.\nDrive technical discussions related to performance methodology, architectural assumptions, workload behavior, scalability analysis, and bottleneck identification.\nReview architectural proposals and provide performance-driven feedback.\nPresent performance studies, technical findings, and architectural recommendations to engineering leadership.\nInfluence product and architecture decisions through data-backed analysis and sound engineering judgment.\nAct as a key technical bridge between architecture, modeling, and performance analysis organizations.\n________________________________________\n6. Methodology Development and Team Growth\nDrive improvements in modeling methodologies, simulation efficiency, and analysis workflows.\nIdentify opportunities for automation across modeling, validation, performance analysis, and reporting activities.\nEstablish best practices for model quality, performance characterization, and architectural analysis.\nContribute to technical mentoring and knowledge sharing across the team.\nSupport the development of junior engineers and future team growth initiatives.\nHelp cultivate a culture of technical excellence and continuous improvement.Qualifications:\nMinimum Qualifications\nEducation\nBachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, Electronics Engineering.\nTechnical Experience\n15+ years of industry experience in performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or related domains.\nStrong software development experience in C++.\nWorking proficiency in Python for automation, performance analysis, data processing, and visualization.\nHands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.\nExperience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or complex hardware systems.\nStrong understanding of:\no SoC architecture\no Memory subsystem architecture\no Memory controllers\no Cache hierarchies\no Data movement architectures\no On-chip communication fabrics and NoC concepts\no High-speed interconnects\no Scale-up and scale-out communication architectures\no Performance bottleneck analysis\no Latency and bandwidth characterization\nExperience performing architectural tradeoff analysis and performance characterization studies.\nExperience working with large performance datasets and deriving meaningful engineering insights.\nAnalytical and Problem-Solving Skills\nStrong debugging and root-cause analysis capabilities.\nAbility to identify performance bottlenecks and drive optimization recommendations.\nExperience developing validation strategies and performance evaluation methodologies.\nStrong quantitative reasoning and data-driven decision-making skills.\nDemonstrated ability to independently solve complex technical problems.\nCommunication and Collaboration\nStrong verbal and written communication skills.\nAbility to collaborate effectively across globally distributed engineering organizations.\nStrong technical presentation and stakeholder management skills.\nAbility to influence engineering decisions through rigorous analysis and technical credibility.\nProven ability to operate independently and deliver results in ambiguous problem spaces.\n________________________________________\nPreferred Qualifications\nDeep understanding of AI accelerator architectures and modern AI infrastructure.\nExperience modeling memory, communication, interconnect, or scalability-related subsystems.\nExperience with Network-on-Chip (NoC) architectures and interconnect performance analysis.\nUnderstanding of scale-up and scale-out architectures used in modern AI computing platforms.\nFamiliarity with AI/ML workloads, large language models, distributed training, and inference environments.\nExperience with performance stimulus generation methodologies and workload characterization.\nExperience building automated dashboards and reporting solutions using Power BI, Tableau, Grafana, Plotly, or similar technologies.\nExperience evaluating large-scale distributed AI systems and accelerator clusters.\n• Experience mentoring engineers and providing technical leadership in cross-functional environments.\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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