{"id":4245107,"url":"https://alion.io/job/intel-silicon-packaging-design-engineer-2","title":"Silicon Packaging Design Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":111,"ghost_share":0.027,"stale_share":0.586,"repost_share":0.036,"time_to_fill_p50_days":30,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Chandler, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"ANSYS","optional":true},{"name":"Ansys HFSS","optional":true},{"name":"AutoCAD","optional":true},{"name":"C++","optional":true},{"name":"Cadence Allegro","optional":true},{"name":"HyperLynx","optional":true},{"name":"Mentor Xpedition","optional":true},{"name":"Python","optional":true},{"name":"SolidWorks","optional":true}],"status":"live","first_seen_at":"2026-11-12T00:00:00Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-13T12:29:15Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Details:\nJob Description:\nThe Opportunity\nJoin Intel's advanced packaging team and help shape the future of high-performance computing. As a Silicon Packaging Design Engineer, you will be responsible for the design and development of next-generation package substrates that enable industry-leading semiconductor products. Working closely with silicon, signal integrity, power delivery, manufacturing, and hardware teams, you will drive substrate solutions from initial concept through tapeout, balancing electrical performance, manufacturability, cost, and schedule requirements.\nThis role offers the opportunity to influence cutting-edge packaging technologies that support Intel's most advanced products and platforms.\nKey Responsibilities\nDesign and develop microelectronic package substrates from architecture definition through final tapeout.\nCreate and optimize physical package layouts, including high-density routing solutions that meet electrical, mechanical, thermal, and manufacturability requirements.\nPerform substrate feasibility, fit, and routing studies to evaluate design tradeoffs involving performance, complexity, cost, and schedule.\nDefine, implement, and maintain substrate design rules while conducting design reviews with internal and external stakeholders.\nAnalyze and resolve design rule check (DRC) violations and other layout-related issues to ensure design quality and robustness.\nCollaborate with silicon, package, board, signal integrity, power integrity, and manufacturing teams to optimize pinouts and system-level connectivity.\nDrive continuous improvements in package design methodologies, automation, and best practices.\nGenerate and maintain design documentation, technical reports, and engineering deliverables within product lifecycle management systems.\nSupport package bring-up, qualification, and debug activities as needed.\nQualifications:\nThe Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications\nUS Citizenship required.\nAbility to obtain US Government TS/SCI Security Clearance.\nBachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related engineering discipline and 6+ months of experience.\nExperience or academic exposure with microelectronic package or PCB physical layout design and manufacturing process.\nExperience with with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.\nExperience with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.\nPreferred Qualifications\nPost Graduate degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related engineering discipline.\nActive US Government TS/SCI Security Clearance.\nExperience with semiconductor package substrate design, package I/O planning, and high-density routing technologies.\nKnowledge of advanced packaging technologies such as flip-chip, 2.5D, 3D packaging, chiplets, embedded bridge, or high-bandwidth interconnect solutions.\nFamiliarity with package electrical analysis and simulation tools including HyperLynx, PowerDC, Ansys HFSS, and Ansys Q3D.\nExperience using package automation and productivity tools such as Package Layout Automation (PLA) and FIELD.\nProgramming or scripting experience using Python, VB, C/C++, or similar languages to drive design automation and workflow improvements.\nProven ability to troubleshoot complex design challenges and develop innovative engineering solutions in a fast-paced environment.\nWhy Intel\nAt Intel, you'll work alongside world-class engineers developing technologies that power everything from artificial intelligence and cloud computing to next-generation client and edge platforms. You'll have the opportunity to solve complex technical challenges, influence leading-edge products, and accelerate your career while helping shape the future of semiconductor innovation\nJob Type:\nExperienced HireShift:\nShift 1 (United States of America)Primary Location:\nUS, Arizona, PhoenixAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/ABenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.\nAnnual Salary Range for jobs which could be performed in the US: $91,150.00-172,860.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":6348,"description_truncated":false,"requirements":{"experience_years_min":1,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Packaging & Labeling","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-13T12:29:15Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 2,029 · green card filings: 490","filings_12m":2029,"filings_prev_12m":3014,"green_card_filings_12m":490,"median_offered_wage_usd":134832,"route":null,"cap_exempt":false,"checked_at":"2026-11-12T07:36:15+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":728}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":1,"expected_fill_days":30,"reasons":["conf:1","win:early","comp:junior,brand"],"computed_at":"2026-11-13T14:13:20Z"},"pay":null,"html_url":"https://alion.io/job/intel-silicon-packaging-design-engineer-2","json_url":"https://alion.io/job/intel-silicon-packaging-design-engineer-2.json","meta":{"generated_at":"2026-11-13T14:13:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28461,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-silicon-packaging-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-silicon-packaging-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-silicon-packaging-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-silicon-packaging-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-silicon-packaging-design-engineer-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4245107}},{"tool":"search_jobs","arguments":{"company":"intel.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4245107},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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