{"id":4245108,"url":"https://alion.io/job/intel-soc-verification-engineer-design-for-debugdesign-for-test","title":"SoC Verification Engineer - Design for Debug/Design For Test","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":111,"ghost_share":0.027,"stale_share":0.586,"repost_share":0.036,"time_to_fill_p50_days":30,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Tessent","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-13T12:29:15Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-13T12:29:15Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Details:\nJob Description:\nCome join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD) and Design for Test ( DFT ).\nAs a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.\nYour responsibilities will include but not be limited to:\n- Validation of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA\n- Validation of Design for Test features like TAP, SCAN and so on.\n- Knowledge on Tessent tools will be a plus\n- Development of testcases in Python for Emulation platform\n- Post-si support\n- Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide\n- Learning the Power Management, Memory and SoC debug architecture and microarchitecture by debugging failures to the root cause\n- Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design\n- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models\n- Developing debugging tools and software\nQualifications:\nMinimum Qualifications:\nCandidate must have either a BS or MS in Computer Science, Computer Engineering or Electrical Engineering.\n- Extensive Pre-silicon and Post-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others\n- Proven record of working across validation teams to solve problems\n- Expert of HW and SW Interaction and debug to root cause\n- Experience working across validation, architecture, SW, design teams and Post-Si to resolve debug issues\n- Minimum 4 yrs experience with DFD/DFT \n- Minimum 8 yrs experience with writing validation plans and software to implement those validation plans \n- Minimum 4 yrs experience with Programming languages/Scripting: C, Python, Verilog and System Verilog\n- Minimum 4 yrs experience with computer architecture\nPreferred Qualifications:\n- 4yrs+ experience with Design for Debug/Design for Test \n- 4yrs+ experience with validation or testing experience\n- 3yrs+ experience with industry standards such as ATB, Core sight, JTAG\n- Experience with Tessent tool would be a plus\n- 2+ experience in Emulation and Post-Si support\nJob Type:\nExperienced HireShift:\nShift 1 (India)Primary Location:\nIndia, BangaloreAdditional Locations:\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. 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