{"id":2985999,"url":"https://alion.io/job/intel-staff-emib-t-substrate-yield-engineer","title":"Staff EMIB-T Substrate Yield Engineer","company":{"id":35,"name":"Intel","domain":"intel.com","url":"https://alion.io/company/intel","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":88,"ghost_share":0.034,"stale_share":0.523,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Semiconductors","role_family":"Semiconductors","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Taipei, Taiwan","Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Computer Vision","optional":false},{"name":"Statistical Process Control","optional":false},{"name":"Photolithography","optional":true}],"status":"live","first_seen_at":"2026-10-16T00:00:00Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-24T03:51:18Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Job Details:\nJob Description:\nIntel's APTM organization is seeking a highly driven Staff Technology Development Substrate Yield Engineer to drive supplier yield, defect reduction, technical issue closure, and process-control maturity supporting next-generation EMIB-T substrates across Taiwan suppliers. The team will be chartered to lead yield performance for next-generation advanced packaging technologies, including EMIB-T (Embedded Multi-die Interconnect Bridge with TSV), Intel's most advanced platform for heterogeneous integration partnering with substrate suppliers locally at the HVM factories. This is a high-visibility, high-accountability role with significant responsibility for enabling successful technology development and manufacturing readiness across both Intel Foundry Services (IFS) and Intel Product Groups (IPG).\nThe ideal candidate is a self-starter who thrives in ambiguous and fast-paced environments, proactively drives issues to closure, and requires minimal supervision. Success in this role requires strong technical depth, urgency in execution, the ability to influence cross-functional teams and suppliers, and a relentless focus on delivering yield and program milestones. \nKey responsibilities\nOwn day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas.\nLead structured investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment.\nUse statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time.\nEstablish clear supplier actions, owners, completion criteria, control limits, and verification plans.\nSupport DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics.\nCapture reusable learning and communicate facts, hypotheses, decisions, and residual risks clearly.\nQualifications:\nMinimum qualificationsMasters degree with 4+years or PhD with 2+years in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline.\n4+ years of experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field.\nHands-on experience in substrate, advanced packaging, or semiconductor yield engineering, including statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution.\nStrong analytical and problem-solving skills with the ability to make data-driven decisions in complex environments.\nExperience working across multiple organizations and influencing stakeholders to achieve results.\nDemonstrated ability to independently manage complex technical issues, execute with urgency, and drive actions to closure.\nExperience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems.\nProfessional proficiency in Mandarin and English sufficient for technical work, subject to HR validation.\nPreferred qualifications\nExperience working directly with substrate suppliers and external manufacturing partners.\nDemonstrated program leadership experience, including coordinating cross-functional technical teams and driving execution in high-visibility, high-impact environments.\nExperience with semi-additive processing, build-up films, micro vias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration.\nPrior experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies.\nExperience with automated data pipelines, dashboards, image analytics, computer vision, AI/ML defect detection, or automated defect classification.\nJob Type:\nExperienced HireShift:\nShift 1 (Taiwan)Primary Location:\nTaiwan, TaipeiAdditional Locations:\nTaiwan, HsinchuPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust\nN/AWork Model for this Role\nThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*\nADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.","description_format":"text","description_chars":5212,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"Taiwan","iso":"TW","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T08:25:14Z"}],"visa":[],"liveness":{"score":68,"band":"ok","label":"Likely open","p_open":1,"p_active":0.682,"p_room":1,"age_days":8,"expected_fill_days":30,"reasons":["conf:2","stale_co","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/intel-staff-emib-t-substrate-yield-engineer","json_url":"https://alion.io/job/intel-staff-emib-t-substrate-yield-engineer.json","meta":{"generated_at":"2026-10-24T15:55:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22944,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":35},"rest":"https://alion.io/mcp/rest/get_company?id=35"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fintel-staff-emib-t-substrate-yield-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fintel-staff-emib-t-substrate-yield-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fintel-staff-emib-t-substrate-yield-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/intel-staff-emib-t-substrate-yield-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fintel-staff-emib-t-substrate-yield-engineer"}]}