{"id":652397,"url":"https://alion.io/job/k2-space-principal-asic-design-verification-engineer","title":"Principal ASIC Design Verification Engineer","company":{"id":171840,"name":"K2 Space","domain":"k2space.com","url":"https://alion.io/company/k2-space","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":85,"open_postings":197,"ghost_share":0.173,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":88,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Seattle, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":190000,"max":285000,"currency":"USD","period":"year","gross":null,"usd_annual":285000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"CI/CD","optional":false},{"name":"Formal Verification","optional":false},{"name":"Git","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-06-30T23:47:21Z","employer_posted_date":"2026-07-01","last_verified_at":"2026-10-14T10:35:38Z","board_verified":true,"closed_at":null,"days_open":105,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":105},"description":"K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price - and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.\nThe rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.\nWith multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger - helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.\nThe Role \nWe are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. \nResponsibilities \nDevelop and execute verification plans for block-level, subsystem-level, and full-chip environments.\nBuild SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.\nWrite SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.\nDrive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.\nRun simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.\nImplement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.\nManage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.\nParticipate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.\nWork closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.\nSupport silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.\nParticipate in ASIC team interviews.\nDrive advancement of DV methodologies and improvements.\nManage external IP providers and verification partners when needed.\nTake lead on large and/or complex systems. \nQualifications \nB.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.\n10+ years of experience in ASIC/SoC verification.\nSolid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.\nProficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).\nExperience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.\nExperience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.\nExperience with developing and integrating reference models.\nExperience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).\nUnderstanding of many industry-standard interfaces (ex: APB/AHB/AXI).\nInvolvement in post-silicon validation planning and execution. \nNice to Have\nExperience with low power verification.\nExperience with analog behavioral models.\nFamiliarity with physical design flows.\nExperience working in cross-functional, geographically distributed teams.\nExperience in space, telecom, or RF/digital mixed systems is a plus. \nCompensation and Benefits:\nBase salary range for this role is $190,000 - $285,000 + equity in the company\nSalary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level\nComprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks\nIf you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!\nIf you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.\nExport Compliance\nAs defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”\nThe person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.\nEqual Opportunity\nK2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.","description_format":"text","description_chars":6324,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Life insurance","Parental leave"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Space & Aerospace","Satellite Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-10T20:35:41Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.738,"p_room":0.44,"age_days":105,"expected_fill_days":88,"reasons":["conf:0","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":{"stated_usd_annual":285000,"is_top_pay":true},"html_url":"https://alion.io/job/k2-space-principal-asic-design-verification-engineer","json_url":"https://alion.io/job/k2-space-principal-asic-design-verification-engineer.json","meta":{"generated_at":"2026-10-14T12:59:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15928,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":171840},"rest":"https://alion.io/mcp/rest/get_company?id=171840"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fk2-space-principal-asic-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fk2-space-principal-asic-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fk2-space-principal-asic-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/k2-space-principal-asic-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fk2-space-principal-asic-design-verification-engineer"}]}