{"id":2266074,"url":"https://alion.io/job/kandou-analog-design-engineer","title":"Analog Design Engineer","company":{"id":3840688,"name":"Kandou","domain":"kandou.ai","url":"https://alion.io/company/kandou-2","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Saint-Sulpice, Switzerland","United Kingdom"],"countries":["CH","GB"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":116000,"max_usd":198000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":8},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false}],"status":"live","first_seen_at":"2026-08-19T13:01:21Z","employer_posted_date":"2026-08-19","last_verified_at":"2026-10-23T19:38:30Z","board_verified":true,"closed_at":null,"days_open":65,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":65},"description":"At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable adoption.\nOur proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency - unlocking unprecedented efficiency for AI training and inference at scale.\nKandou’s architecture is not just an incremental improvement - it’s a foundational shift in how AI hardware is built for the future.\nJob title: Analog Design Engineer\nLocation: EU/CH/UK\nKey Responsibilities\nPosition in design, modeling, and verification of custom analog designs for high-speed Serdes transceivers in advanced technology nodes\n\nDesign and verification of analog circuits, following prescribed design and documentation flows, to meet architecture specifications\n\nIf necessary, support and interact with customers on requirements, design specifications, performance results and product delivery\n\nSupport analog IP and chip level integration\n\nCollaborate with architects, technical leads, analog and digital design, layout, integration, verification, silicon validation and quality teams as needed\n\nCompetencies\nSkilled in the design of high speed analog serdes circuits including DFT, DFM and ESD protection, with a deep knowledge of transistor and wireline communications fundamentals\n\nUnderstanding of layout approaches and design techniques used for high-speed and high precision circuits\n\nAdvanced user of EDA tools for design and verification of analog circuits, preferably using the Cadence Virtuoso environment, including their use for simulation, parasitic extraction, electromagnetic modelling, EM/IR and reliability analysis as well as LVS and DRC\n\nSelf-motivated, a strong sense of ownership and responsibility with good verbal and written communication skills and a team player\n\nAbility to manage and complete designs to schedule using defined design process flows as well as reporting design status to internal management team\n\nRequirements\nThe candidate should have a Master's or Ph.D. degree in Electronics or other relevant fields\n\nMinimum 5 years of experience in analog design and layout of key circuits in multi-gigabit serial data-link transceivers or RF multi tone communications such as equalizers, clock generators, clock and data recovery circuits, TISAR ADC’s, serialisers and output drivers etc.\n\nExpertise in design and layout of high-speed circuits such as oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, amplifiers, buffers, regulators, filters, ADC, DAC etc.\n\nExperience with modern semiconductor process technologies, preferably in finFet technology nodes\n\nExperience using Ocean, MDL or equivalent to automate analog design verification is highly desirable\n\nIf this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!\nVisit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/","description_format":"text","description_chars":3290,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United Kingdom","iso":"GB","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Memory & Storage Chips"],"lifecycle":[{"event":"open","at":"2026-10-11T06:33:18Z"}],"visa":[],"liveness":{"score":18,"band":"cold","label":"Long shot","p_open":1,"p_active":0.64,"p_room":0.28,"age_days":64,"expected_fill_days":20,"reasons":["conf:0","velocity","win:tail","crowd:"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/kandou-analog-design-engineer","json_url":"https://alion.io/job/kandou-analog-design-engineer.json","meta":{"generated_at":"2026-10-23T23:21:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":6685,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3840688},"rest":"https://alion.io/mcp/rest/get_company?id=3840688"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fkandou-analog-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fkandou-analog-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fkandou-analog-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/kandou-analog-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fkandou-analog-design-engineer"}]}