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Salary
≈ $28k – $58k per year (Estimated)
Location
In office (Hyderabad)
Seniority
Principal · 12+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 11, 2026. First seen by Alion on Sep 11, 2026.

Overview
Company
Impact
Profile match
Revolutionary Copper MIMO technology eliminates costly HBM chips. 10X lower cost, 3X lower power, 8X more scale for next-gen AI systems and connectivity.

Key Responsibilities:

  • Lead DFT activity for the next generation products

  • Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes, DDR, PCIe designs

  • Closely working with Physical implementation team to define timing constraints in test modes and helping to converge for successful tapeout

  • Good understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development

  • Define the test plan by closely working with the design teams and drive the pattern development of functional/structural tests for final/wafer test program

  • Closely working with the cross functional teams to bring up device qualification solution for HTOL

  • Drive lab bench silicon debug to understand ATE bring up issues

Skills:

  • Excellent communication skills, and strong team player with can do type of attitude

  • Mentoring the team members

  • Excellent debugging skills

  • Process oriented to drive automation to help increase productivity and quality

Qualifications:

  • 12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation

  • Proven track record of delivering DFT solution to complex designs

  • Experience working with IJTAG methodologies, understanding device functionality

  • Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies

  • Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics

  • Strong debug capabilities in simulating patterns with timing

  • Experience in defining test mode constraints and analyzing the timing reports

  • Experience with industry standard EDA tools for DFT, timing, and simulation

  • Good knowledge of System Verilog

  • Experience with chiplet based designs is a plus

Education:

  • Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering or similar fields (equivalent or higher)

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