{"id":2266038,"url":"https://alion.io/job/kandou-dft-full-time","title":"DFT - Full Time","company":{"id":3840688,"name":"Kandou","domain":"kandou.ai","url":"https://alion.io/company/kandou-2","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, 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successful tapeout\n\nGood understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development\n\nDefine the test plan by closely working with the design teams and drive the pattern development of functional/structural tests for final/wafer test program\n\nClosely working with the cross functional teams to bring up device qualification solution for HTOL\n\nDrive lab bench silicon debug to understand ATE bring up issues\n\nSkills:\nExcellent communication skills, and strong team player with can do type of attitude\n\nMentoring the team members\n\nExcellent debugging skills\n\nProcess oriented to drive automation to help increase productivity and quality\n\nQualifications:\n12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation\n\nProven track record of delivering DFT solution to complex designs\n\nExperience working with IJTAG methodologies, understanding device functionality\n\nExperience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies\n\nExperience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics\n\nStrong debug capabilities in simulating patterns with timing\n\nExperience in defining test mode constraints and analyzing the timing reports\n\nExperience with industry standard EDA tools for DFT, timing, and simulation\n\nGood knowledge of System Verilog\n\nExperience with chiplet based designs is a plus\n\nEducation:\nBachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering or similar fields (equivalent or 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