{"id":2266063,"url":"https://alion.io/job/kandou-silicon-validation-manager","title":"Silicon Validation Manager","company":{"id":3840688,"name":"Kandou","domain":"kandou.ai","url":"https://alion.io/company/kandou-2","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":53000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":18,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"BERT","optional":false},{"name":"CI/CD","optional":false},{"name":"OpenOCD","optional":false},{"name":"Python","optional":false},{"name":"Robot Framework","optional":false}],"status":"live","first_seen_at":"2026-08-19T13:08:23Z","employer_posted_date":"2026-08-19","last_verified_at":"2026-10-12T06:22:35Z","board_verified":true,"closed_at":null,"days_open":53,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":53},"description":"Kandou is a semiconductor company pioneering high-performance interconnect and chip-to-chip communication solutions. Our engineering teams push the boundaries of what is possible in silicon design, validation, and system integration. We are looking for a seasoned Silicon Validation Lead to join our R&D organization and drive end-to-end validation of complex SoC platforms.\nSilicon Validation Manager\nLocation: Hyderabad\nDepartment: Silicon Engineering / Hardware Validation\nEmployment Type: Full-Time\nRole Overview\nAs the Silicon Validation Director/Manager, you will own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms that integrate PCIe, CXL, DDR5, RISC-V processors, Memory Fabric, PCIe Switch, and Caliptra Root of Trust (RoT) subsystems. You will lead a cross-functional validation team, define test strategies, and act as the primary technical interface between design, architecture, firmware, and system teams to ensure first-pass silicon quality and robust production readiness.\nKey Responsibilities\nSilicon Bring-Up & Validation\nLead pre- and post-silicon validation for complex SoCs encompassing PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5 memory subsystems, RISC-V processor cores, Memory Fabric, PCIe Switch, and Caliptra RoT IP.\n\nDrive silicon bring-up from power-on through full functional validation, characterization, and compliance testing.\n\nDevelop and own comprehensive silicon validation plans, test coverage matrices, and sign-off criteria aligned with tapeout and production milestones.\n\nExecute and manage compliance and interoperability testing against PCIe, CXL, JEDEC DDR5, and relevant security/RoT standards.\n\nTest Architecture & Strategy\nDefine test infrastructure architecture: board-level bring-up environments, FPGA prototypes, simulation correlation, and lab automation frameworks.\n\nDrive development of validation collateral including test plans, test suites, regression frameworks, and pass/fail criteria for all integrated subsystems.\n\nEstablish coverage tracking dashboards and triage processes to systematically reduce validation escapes.\n\nDebug & Root Cause Analysis\nLead deep-dive debugging of complex multi-layer failures spanning RTL, firmware, hardware, and system software.\n\nUtilize protocol analyzers, logic analyzers, oscilloscopes, and CXL/PCIe test equipment (e.g., Teledyne LeCroy, Keysight, Spirent) to isolate and characterize issues.\n\nAuthor and maintain detailed bug reports, failure analysis documents, and errata for silicon revisions.\n\nTeam Leadership & Collaboration\nLead and mentor a team of validation engineers; set technical direction, review deliverables, and foster a culture of engineering rigor.\n\nCollaborate closely with RTL design, DV, firmware, and software teams to ensure seamless hand-off from pre-silicon simulation to physical silicon validation.\n\nInterface with external IP vendors, OEM/ODM partners, and compliance labs for interoperability and certification activities.\n\nRepresent the validation team in architecture reviews, design reviews, and program planning meetings.\n\nProcess & Continuous Improvement\nChampion test automation and CI/CD integration for regression management.\n\nDrive lessons-learned processes across silicon spins and contribute to validation methodology improvements.\n\nEstablish and maintain lab safety, equipment inventory, and test asset management best practices.\n\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.\n\n18+ years of hands-on silicon validation or hardware validation engineering experience, with at least 6 years in a Manager/Lead or staff-level role.\n\nDeep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer characterization, and debug.\n\nStrong hands-on experience with CXL (1.1 / 2.0 / 3.0): memory semantic protocols, device types (Type 1/2/3), coherency mechanisms, and interoperability testing.\n\nExtensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC compliance, and RAS features.\n\nSolid experience with RISC-V processor bring-up, ISA compliance validation, and core/cluster debug using JTAG and hardware debug probes.\n\nHands-on experience with Memory Fabric architectures: bandwidth/latency characterization, coherency validation, and fabric stress testing.\n\nExperience validating PCIe Switch silicon: multi-port topologies, QoS, hot-plug, and error-handling scenarios.\n\nExperience with Caliptra Root of Trust or equivalent security subsystem validation: secure boot, firmware attestation, cryptographic engine verification, and DICE/RoT compliance.\n\nTechnical Skills\nProtocols: PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5, AXI, APB, AMBA\n\nProcessor: RISC-V (RV64GC, RISC-V Debug Spec), JTAG\n\nSecurity: Caliptra RoT, Secure Boot, DICE, TPM concepts\n\nInterconnect: Memory Fabric, PCIe Switch, NoC fundamentals\n\nInstrumentation: Protocol analyzers, BERT, oscilloscopes, VNAs\n\nAutomation: Python, Tcl, Bash, PyATS, Robot Framework\n\nEDA / Debug: Signal Tap, ChipScope, OpenOCD, GDB\n\nWhat We Offer\nOpportunity to work on cutting-edge, industry-defining interconnect and semiconductor technology.\n\nCollaborative, high-trust engineering culture with direct access to architecture and design teams.\n\nCompetitive compensation, equity participation, and comprehensive benefits.\n\nFlexible work arrangements and a commitment to continued technical growth.\n\nKandou is an equal opportunity employer. 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