{"id":2256329,"url":"https://alion.io/job/keysight-asic-design-for-test-dft-engineer-intern","title":"ASIC Design-for-Test (DFT) Engineer Intern","company":{"id":53596,"name":"Keysight","domain":"keysight.com","url":"https://alion.io/company/keysight","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Colorado Springs, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":72000,"max_usd":216000,"period":"year","method":null,"sample_n":3534},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":true},{"name":"Linux","optional":true},{"name":"Python","optional":true},{"name":"Ruby","optional":true},{"name":"Synopsys TestMAX","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Tessent","optional":true},{"name":"Unix","optional":true},{"name":"Verilog","optional":true},{"name":"VHDL","optional":true}],"status":"live","first_seen_at":"2026-09-15T20:47:00Z","employer_posted_date":"2026-10-11","last_verified_at":"2026-10-12T01:12:29Z","board_verified":true,"closed_at":null,"days_open":26,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":26},"description":"OverviewKeysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.\nOur award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.\nJob Description\nKeysight Technologies has an exciting opportunity for an ASIC Design-for-Test (DFT) Engineer Intern within our ASIC R&D organization. This role provides hands-on experience across the semiconductor product development lifecycle, with a focus on Design-for-Test (DFT) methodologies used to ensure the manufacturability, quality, and reliability of advanced integrated circuits.\nWorking alongside experienced ASIC Test Engineers, you will gain exposure to industry-standard EDA tools and flows used for scan insertion, ATPG pattern generation, memory test, silicon validation, and production test development. This internship is an excellent opportunity for students interested in digital design, VLSI, semiconductor development, and hardware engineering to gain practical experience on real ASIC programs.\nAs an intern, you will collaborate with ASIC design, verification, physical design, and test engineers while contributing to projects that directly impact the successful development and release of next-generation semiconductor products.\nThis position is based in Colorado Springs, Colorado, consistently recognized as one of the nation's most desirable places to live.\nResponsibilities\nResponsibilities\nSupport the development and verification of DFT architectures for complex digital and mixed-signal ASICs\nLearn and apply industry-standard DFT methodologies, including scan insertion, scan compression, ATPG, Streaming Scan Networks, and memory BIST (MBIST)\nAssist with ATPG pattern generation, coverage analysis, and debug using Siemens Tessent and other industry-standard EDA tools\nDevelop scripts and automation solutions using Python, Ruby, Tcl, or similar languages to improve engineering workflows and data analysis\nCollaborate with ASIC design, verification, physical design, and product engineering teams to ensure testability requirements are incorporated throughout the design lifecycle\nParticipate in silicon bring-up, characterization, debug, and failure analysis activities\nAnalyze test results and help develop solutions to improve test quality, coverage, and efficiency\nQualifications\nBasic Qualifications\nCurrently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field\nCompletion of sophomore year or higher by Summer 2027\nCoursework in Digital Logic Design, Computer Architecture, VLSI Design, FPGA Design, or related areas\nUnderstanding of digital circuits, finite state machines, and computer hardware fundamentals\nProgramming or scripting experience in Python, C/C++, Tcl, Ruby, or similar languages\nStrong analytical, problem-solving, and debugging skills\nDemonstrated ability to work effectively in a collaborative team environment\nDesired Qualifications\nStrong Interest in semiconductor design, ASIC development, hardware verification, or Design-for-Test (DFT) methodologies\nFamiliarity with Verilog, SystemVerilog, or VHDL\nKnowledge of Linux/Unix environments and scripting\nExposure to ASIC design flows, RTL development, simulation, or verification\nFamiliarity with DFT concepts such as scan chains, ATPG, boundary scan, test compression, or memory BIST\nExposure to EDA tools such as Siemens Tessent, Synopsys TestMAX, Cadence Modus, or similar tools\nStrong written and verbal communication skills\nDemonstrated ability to work independently while managing multiple technical tasks and priorities\nCO Pay Range\nBachelors- $33.28-$35.83\nMasters-$40.06-43.14\nNote: For other locations, pay ranges will vary by region.\nBased on experience, education and skills, most offers will be between the minimum and the midpoint of the Salary Range listed above.\nCandidates who wish to be considered must be enrolled in a accredited college/university as of September 2027. Applicants who have graduated before September 2027 will not be considered unless they are starting a MS or PHD program after graduating.\nVisa Sponsorship is not available for this position. Candidates who now or at any point in the future require sponsorship for employment visa status (e.g., H-1B Visa status) may not be considered.\nCareers Privacy Statement Keysight is an Equal Opportunity Employer.\nKeysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.\nResponsibilities\nSupport the development and verification of DFT architectures for complex digital and mixed-signal ASICs\nLearn and apply industry-standard DFT methodologies, including scan insertion, scan compression, ATPG, Streaming Scan Networks, and memory BIST (MBIST)\nAssist with ATPG pattern generation, coverage analysis, and debug using Siemens Tessent and other industry-standard EDA tools\nDevelop scripts and automation solutions using Python, Ruby, Tcl, or similar languages to improve engineering workflows and data analysis\nCollaborate with ASIC design, verification, physical design, and product engineering teams to ensure testability requirements are incorporated throughout the design lifecycle\nParticipate in silicon bring-up, characterization, debug, and failure analysis activities\nAnalyze test results and help develop solutions to improve test quality, coverage, and efficiency\nBasic Qualifications\nCurrently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field\nCompletion of sophomore year or higher by Summer 2027\nCoursework in Digital Logic Design, Computer Architecture, VLSI Design, FPGA Design, or related areas\nUnderstanding of digital circuits, finite state machines, and computer hardware fundamentals\nProgramming or scripting experience in Python, C/C++, Tcl, Ruby, or similar languages\nStrong analytical, problem-solving, and debugging skills\nDemonstrated ability to work effectively in a collaborative team environment\nDesired Qualifications\nStrong Interest in semiconductor design, ASIC development, hardware verification, or Design-for-Test (DFT) methodologies\nFamiliarity with Verilog, SystemVerilog, or VHDL\nKnowledge of Linux/Unix environments and scripting\nExposure to ASIC design flows, RTL development, simulation, or verification\nFamiliarity with DFT concepts such as scan chains, ATPG, boundary scan, test compression, or memory BIST\nExposure to EDA tools such as Siemens Tessent, Synopsys TestMAX, Cadence Modus, or similar tools\nStrong written and verbal communication skills\nDemonstrated ability to work independently while managing multiple technical tasks and priorities\nCO Pay Range\nBachelors- $33.28-$35.83\nMasters-$40.06-43.14\nNote: For other locations, pay ranges will vary by region.\nBased on experience, education and skills, most offers will be between the minimum and the midpoint of the Salary Range listed above.\nCandidates who wish to be considered must be enrolled in a accredited college/university as of September 2027. Applicants who have graduated before September 2027 will not be considered unless they are starting a MS or PHD program after graduating.\nVisa Sponsorship is not available for this position. Candidates who now or at any point in the future require sponsorship for employment visa status (e.g., H-1B Visa status) may not be considered.\nCareers Privacy Statement Keysight is an Equal Opportunity Employer.\nKeysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.","description_format":"text","description_chars":8516,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Simulation & Digital Twin Software","Custom Software Development"],"lifecycle":[{"event":"open","at":"2026-10-11T03:56:46Z"}],"visa":[],"liveness":{"score":35,"band":"fade","label":"Fading","p_open":1,"p_active":0.639,"p_room":0.55,"age_days":26,"expected_fill_days":18,"reasons":["conf:2","win:tail","comp:junior,brand"],"computed_at":"2026-10-12T04:11:40Z"},"pay":null,"html_url":"https://alion.io/job/keysight-asic-design-for-test-dft-engineer-intern","json_url":"https://alion.io/job/keysight-asic-design-for-test-dft-engineer-intern.json","meta":{"generated_at":"2026-10-12T04:11:40Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":6679,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":53596},"rest":"https://alion.io/mcp/rest/get_company?id=53596"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fkeysight-asic-design-for-test-dft-engineer-intern"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fkeysight-asic-design-for-test-dft-engineer-intern"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fkeysight-asic-design-for-test-dft-engineer-intern"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/keysight-asic-design-for-test-dft-engineer-intern\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fkeysight-asic-design-for-test-dft-engineer-intern"}]}