{"id":2256085,"url":"https://alion.io/job/keysight-eda-aiml-layout-engineering-intern","title":"EDA AI/ML Layout Engineering Intern","company":{"id":53596,"name":"Keysight","domain":"keysight.com","url":"https://alion.io/company/keysight","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Calabasas, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"PyTorch","optional":false},{"name":"PyTorch C++","optional":false},{"name":"Scikit-learn","optional":false},{"name":"TensorFlow","optional":false},{"name":"TensorFlow C++","optional":false},{"name":"Agile","optional":true},{"name":"Git","optional":true},{"name":"Linux","optional":true},{"name":"Reinforcement Learning","optional":true},{"name":"Rust","optional":true},{"name":"Windows","optional":true}],"status":"live","first_seen_at":"2026-09-29T21:54:00Z","employer_posted_date":"2026-10-11","last_verified_at":"2026-10-11T21:36:09Z","board_verified":true,"closed_at":null,"days_open":12,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":12},"description":"OverviewKeysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.\nOur award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.\nResponsibilities\nAt Keysight EDA, we are developing next-generation AI-powered Electronic Design Automation (EDA) technologies to accelerate RFIC and analog IC design. As an EDA AI/ML Layout Engineering Intern, you will contribute to innovative solutions that apply machine learning, optimization, and software engineering to automate layout generation, PCell development, and design space exploration.\nWorking alongside EDA engineers, AI researchers, and RFIC domain experts, you will help develop intelligent workflows that improve designer productivity and accelerate chip development.\nKey Responsibilities\nDevelop AI and ML solutions for RFIC and analog layout automation\nResearch and prototype machine learning techniques for layout synthesis and design optimization\nAssist in the development of parameterized cells (PCells) and layout generation workflows\nWork on geometric, topological, and rule-aware layout generation techniques\nContribute to surrogate modeling and design space exploration frameworks\nBuild data generation, training, and evaluation pipelines for AI-driven EDA workflows\nDevelop software components in Python and potentially C++ under mentorship\nEvaluate AI-assisted design methodologies using real-world semiconductor design problems\nCollaborate with EDA engineers and RFIC designers to validate solutions\nQualifications\nMinimum Qualifications\nCurrently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field\nStrong programming skills in Python\nFamiliarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn\nSolid understanding of data structures, algorithms, and object-oriented programming\nStrong analytical and problem-solving skills\nInterest in AI/ML applied to engineering design automation\nPreferred Qualifications\nCoursework or research in RFIC Design, Analog IC Design, VLSI Physical Design, EDA/CAD, or Semiconductor Design Automation\nFamiliarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation\nExposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques\nExperience with C++, Rust, or performance-oriented software development\nExposure to software development on Windows or Linux platforms\nFamiliarity with Git and modern software development practices\nInterest in AI-assisted schematic generation, layout synthesis, semiconductor design workflows, and next-generation AI-powered EDA tools\nInterest in learning about multithreaded applications and desktop software development\nCuriosity and eagerness to work in an Agile, collaborative team environment\nCA Pay Range\nMaster's: Min $40.32 to Max $43.42\nPhD: Min $40.32 to Max $53.67\nRelocation is available.\nVisa Sponsorship is not available for this position.\nPlease note, candidates must possess valid work authorization for the duration of the internship. International students requiring work authorization should work with their university to obtain and maintain appropriate CPT or other eligible employment authorization prior to the internship start date.\nCareers Privacy Statement ***Keysight is an Equal Opportunity Employer.***\nAt Keysight EDA, we are developing next-generation AI-powered Electronic Design Automation (EDA) technologies to accelerate RFIC and analog IC design. As an EDA AI/ML Layout Engineering Intern, you will contribute to innovative solutions that apply machine learning, optimization, and software engineering to automate layout generation, PCell development, and design space exploration.\nWorking alongside EDA engineers, AI researchers, and RFIC domain experts, you will help develop intelligent workflows that improve designer productivity and accelerate chip development.\nKey Responsibilities\nDevelop AI and ML solutions for RFIC and analog layout automation\nResearch and prototype machine learning techniques for layout synthesis and design optimization\nAssist in the development of parameterized cells (PCells) and layout generation workflows\nWork on geometric, topological, and rule-aware layout generation techniques\nContribute to surrogate modeling and design space exploration frameworks\nBuild data generation, training, and evaluation pipelines for AI-driven EDA workflows\nDevelop software components in Python and potentially C++ under mentorship\nEvaluate AI-assisted design methodologies using real-world semiconductor design problems\nCollaborate with EDA engineers and RFIC designers to validate solutions\nMinimum Qualifications\nCurrently pursuing a Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, Applied Mathematics, or a related technical field\nStrong programming skills in Python\nFamiliarity with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn\nSolid understanding of data structures, algorithms, and object-oriented programming\nStrong analytical and problem-solving skills\nInterest in AI/ML applied to engineering design automation\nPreferred Qualifications\nCoursework or research in RFIC Design, Analog IC Design, VLSI Physical Design, EDA/CAD, or Semiconductor Design Automation\nFamiliarity with layout automation, PCell development, computational geometry, and design-rule-aware layout generation\nExposure to surrogate modeling, Bayesian optimization, reinforcement learning, and design space exploration techniques\nExperience with C++, Rust, or performance-oriented software development\nExposure to software development on Windows or Linux platforms\nFamiliarity with Git and modern software development practices\nInterest in AI-assisted schematic generation, layout synthesis, semiconductor design workflows, and next-generation AI-powered EDA tools\nInterest in learning about multithreaded applications and desktop software development\nCuriosity and eagerness to work in an Agile, collaborative team environment\nCA Pay Range\nMaster's: Min $40.32 to Max $43.42\nPhD: Min $40.32 to Max $53.67\nRelocation is available.\nVisa Sponsorship is not available for this position.\nPlease note, candidates must possess valid work authorization for the duration of the internship. International students requiring work authorization should work with their university to obtain and maintain appropriate CPT or other eligible employment authorization prior to the internship start date.\nCareers Privacy Statement ***Keysight is an Equal Opportunity Employer.***","description_format":"text","description_chars":7218,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["Space & Aerospace","Simulation & Digital Twin Software","Custom Software Development"],"lifecycle":[{"event":"open","at":"2026-10-11T03:56:46Z"}],"visa":[],"liveness":{"score":72,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.796,"p_room":0.9,"age_days":12,"expected_fill_days":18,"reasons":["conf:1","win:mid","comp:junior,brand"],"computed_at":"2026-10-11T22:41:24Z"},"pay":null,"html_url":"https://alion.io/job/keysight-eda-aiml-layout-engineering-intern","json_url":"https://alion.io/job/keysight-eda-aiml-layout-engineering-intern.json","meta":{"generated_at":"2026-10-11T22:41:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12826,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":53596},"rest":"https://alion.io/mcp/rest/get_company?id=53596"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fkeysight-eda-aiml-layout-engineering-intern"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fkeysight-eda-aiml-layout-engineering-intern"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fkeysight-eda-aiml-layout-engineering-intern"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/keysight-eda-aiml-layout-engineering-intern\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fkeysight-eda-aiml-layout-engineering-intern"}]}