{"id":3761390,"url":"https://alion.io/job/keysight-rd-dspfpga-design-automation-intern","title":"R&D DSP/FPGA Design Automation Intern","company":{"id":53596,"name":"Keysight","domain":"keysight.com","url":"https://alion.io/company/keysight","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":94,"open_postings":4,"ghost_share":0,"stale_share":0.25,"repost_share":0,"time_to_fill_p50_days":51,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Rosa, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Chisel","optional":false},{"name":"Cocotb","optional":false},{"name":"Digital Twin","optional":false},{"name":"Formal Verification","optional":false},{"name":"Git","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Quantization","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-11-04T17:49:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-05T06:32:16Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"OverviewKeysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~16,800 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.\nOur award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.\nJob Description\nWe are seeking a motivated R&D intern to help develop and demonstrate a scalable, AI-assisted development workflow for FPGA-based digital signal processing systems.\nThis position is well suited to a student who enjoys working across traditional boundaries between signal processing, digital design, and software development. You will gain experience with a complete FPGA development lifecycle while investigating how AI-assisted engineering can improve development speed, reuse, and consistency without replacing sound engineering judgment.\nResponsibilities\nBuild reusable, parameterized FPGA components for DSP, such as MACs, FIFOs, adder trees, coefficient memories, delay elements and numeric conversion blocks.\nTranslate DSP and system requirements into FPGA architecture and implementation specs.\nDesign and verify RTL in Verilog, SystemVerilog, VHDL or an equivalent language.\nWrite bit-accurate or fixed-point reference models to check the FPGA implementations against.\nAssemble the components into a representative streaming DSP subsystem.\nCreate automated simulation and verification tests that cover numerical accuracy, reset behavior, streaming interfaces, backpressure and parameter boundaries.\nSupport synthesis, timing analysis, resource evaluation and optimization.\nUse Python or a similar language to automate design, testing, data collection and reporting.\nInvestigate AI-assisted development tools across FPGA architecture, implementation, verification and documentation. Define objective ways to measure the quality of their output.\nAnalyze results and identify functional, numerical, timing or resource limitations.\nCollaborate with DSP, FPGA, software and system engineers, including in design reviews.\nDocument interfaces, parameter constraints, verification results and findings.\nPresent results and recommendations to the engineering team at the end of the internship.\nQualifications\nRequired\nCurrently pursuing a Bachelor's or Master's in EE, CE, CS or a related field.\nCoursework, project work or job experience in DSP or digital system design.\nUnderstanding of digital logic, synchronous design, pipelining and FSMs.\nExperience with at least one HDL or hardware-construction language (Verilog, SystemVerilog, VHDL or Chisel).\nExperience with Python, MATLAB, C/C++ or a similar language for modeling or automation.\nFamiliarity with fixed-point arithmetic, quantization or numerical implementation of DSP algorithms.\nAbility to turn requirements into an implementable design.\nAbility to analyze technical results and communicate conclusions clearly.\nStrong problem-solving, communication and teamwork skills.\nAbility and desire to learn emerging technologies.\nDesired\nExperience designing, simulating or synthesizing FPGA logic, with Xilinx/AMD, Intel or comparable tools.\nExperience with streaming interfaces (valid/ready, FIFOs, clock domains).\nExperience implementing FIR filters, resamplers, channelizers or other waveform processing.\nExperience writing parameterized, reusable HDL.\nExperience with cocotb, constrained-random testing, assertions or formal verification.\nExperience with Git, CI, automated builds or regression testing.\nExperience building software tools for other engineers.\nExperience using AI-assisted tools for software, HDL, testing or analysis.\nFamiliarity with component metadata, interface contracts, model-based design or digital twins.\nInterest in FPGA tradeoffs among throughput, latency, timing and DSP, memory and logic resources.\nThe level of role will be based on applicable experience, education and skills; most offers will be between the minimum and midpoint of the salary range listed below.\nCA pay range: MIN $41.14 to MAX $44.31\nNote: for other locations, pay ranges will vary by region.\nRelocation is available for this position.\nVisa Sponsorship is not available for this position.\nCareers Privacy Statement ***Keysight is an Equal Opportunity Employer.***\nBuild reusable, parameterized FPGA components for DSP, such as MACs, FIFOs, adder trees, coefficient memories, delay elements and numeric conversion blocks.\nTranslate DSP and system requirements into FPGA architecture and implementation specs.\nDesign and verify RTL in Verilog, SystemVerilog, VHDL or an equivalent language.\nWrite bit-accurate or fixed-point reference models to check the FPGA implementations against.\nAssemble the components into a representative streaming DSP subsystem.\nCreate automated simulation and verification tests that cover numerical accuracy, reset behavior, streaming interfaces, backpressure and parameter boundaries.\nSupport synthesis, timing analysis, resource evaluation and optimization.\nUse Python or a similar language to automate design, testing, data collection and reporting.\nInvestigate AI-assisted development tools across FPGA architecture, implementation, verification and documentation. Define objective ways to measure the quality of their output.\nAnalyze results and identify functional, numerical, timing or resource limitations.\nCollaborate with DSP, FPGA, software and system engineers, including in design reviews.\nDocument interfaces, parameter constraints, verification results and findings.\nPresent results and recommendations to the engineering team at the end of the internship.\nRequired\nCurrently pursuing a Bachelor's or Master's in EE, CE, CS or a related field.\nCoursework, project work or job experience in DSP or digital system design.\nUnderstanding of digital logic, synchronous design, pipelining and FSMs.\nExperience with at least one HDL or hardware-construction language (Verilog, SystemVerilog, VHDL or Chisel).\nExperience with Python, MATLAB, C/C++ or a similar language for modeling or automation.\nFamiliarity with fixed-point arithmetic, quantization or numerical implementation of DSP algorithms.\nAbility to turn requirements into an implementable design.\nAbility to analyze technical results and communicate conclusions clearly.\nStrong problem-solving, communication and teamwork skills.\nAbility and desire to learn emerging technologies.\nDesired\nExperience designing, simulating or synthesizing FPGA logic, with Xilinx/AMD, Intel or comparable tools.\nExperience with streaming interfaces (valid/ready, FIFOs, clock domains).\nExperience implementing FIR filters, resamplers, channelizers or other waveform processing.\nExperience writing parameterized, reusable HDL.\nExperience with cocotb, constrained-random testing, assertions or formal verification.\nExperience with Git, CI, automated builds or regression testing.\nExperience building software tools for other engineers.\nExperience using AI-assisted tools for software, HDL, testing or analysis.\nFamiliarity with component metadata, interface contracts, model-based design or digital twins.\nInterest in FPGA tradeoffs among throughput, latency, timing and DSP, memory and logic resources.\nThe level of role will be based on applicable experience, education and skills; most offers will be between the minimum and midpoint of the salary range listed below.\nCA pay range: MIN $41.14 to MAX $44.31\nNote: for other locations, pay ranges will vary by region.\nRelocation is available for this position.\nVisa Sponsorship is not available for this position.\nCareers Privacy Statement ***Keysight is an Equal Opportunity Employer.***","description_format":"text","description_chars":7997,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["EDA Software","Simulation & Digital Twin Software","Test & Measurement Instruments"],"lifecycle":[{"event":"open","at":"2026-11-04T18:40:55Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":51,"reasons":["conf:4","velocity","win:early","comp:junior,brand"],"computed_at":"2026-11-05T05:54:30Z"},"pay":null,"html_url":"https://alion.io/job/keysight-rd-dspfpga-design-automation-intern","json_url":"https://alion.io/job/keysight-rd-dspfpga-design-automation-intern.json","meta":{"generated_at":"2026-11-05T09:38:42Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12249,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-06T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":53596},"rest":"https://alion.io/mcp/rest/get_company?id=53596"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fkeysight-rd-dspfpga-design-automation-intern"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fkeysight-rd-dspfpga-design-automation-intern"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fkeysight-rd-dspfpga-design-automation-intern"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/keysight-rd-dspfpga-design-automation-intern\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fkeysight-rd-dspfpga-design-automation-intern"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3761390}},{"tool":"search_jobs","arguments":{"company":"keysight.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3761390},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); 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