ASIC RTL Design Engineer

Role : ASIC RTL Design Engineer

About the Role :

We are looking for an experienced ASIC RTL Design Engineer to work on SoC subsystem design, RTL development, and IP integration. The ideal candidate should have strong hands-on experience with SystemVerilog, RTL design, SoC/IP integration, and AMBA protocols, along with exposure to industry-standard RTL quality and verification tools.

You will collaborate closely with architecture, verification, and physical design teams to develop high-quality, scalable, and synthesizable RTL for complex ASIC/SoC designs.

Key Responsibilities :

- Design and develop synthesizable RTL for ASIC/SoC subsystems using Verilog/SystemVerilog.

- Perform IP integration and subsystem-level integration within complex SoC environments.

- Understand and implement AMBA protocols, including AXI, AHB, and APB.

- Work closely with architects and verification engineers to understand specifications and translate them into robust RTL implementations.

- Perform RTL quality checks, including linting, structural analysis, and coding-quality reviews.

- Analyze and resolve RTL issues identified through lint, simulation, synthesis, and integration activities.

- Work with tools such as SpyGlass Lint, Synopsys Design Compiler (DC), Verdi, and Xcelium.

- Participate in RTL design reviews, code reviews, and subsystem integration reviews.

- Debug functional and integration issues and collaborate with cross-functional teams to resolve them.

- Ensure RTL meets design specifications, quality standards, and synthesis requirements.

- Contribute to improving RTL design methodologies, coding standards, and integration processes.

Required Skills & Experience :

- Strong experience in ASIC RTL Design and SoC subsystem development.

- Hands-on expertise in Verilog/SystemVerilog.

- Good understanding of SoC architecture and IP integration.

- Strong knowledge of AMBA bus protocols, particularly AXI/AHB/APB.

- Experience with RTL linting and quality checks, preferably using SpyGlass.

- Experience with logic synthesis and tools such as Synopsys Design Compiler.

- Familiarity with debugging and waveform analysis using Verdi.

- Exposure to Xcelium or other industry-standard simulation tools.

- Good understanding of RTL design methodologies, coding guidelines, and synthesis concepts.

- Strong analytical, debugging, and problem-solving skills.

Good to Have :

- Experience working on complex SoC designs and subsystem/IP integration.

- Knowledge of CDC/RDC analysis and related RTL quality checks.

- Exposure to ASIC verification methodologies and simulation/debug environments.

- Understanding of synthesis constraints and timing-related concepts.

- Experience working in a cross-functional semiconductor development environment.

Education :

- Bachelor's or Master's degree in Computer Engineering, or a related field.

Key Skills : ASIC RTL Design | Verilog | SystemVerilog | SoC | IP Integration | AMBA | AXI | AHB | APB | SpyGlass | Synopsys Design Compiler | Verdi | Xcelium | RTL Linting | RTL Quality Checks | Logic Synthesis

Skills

ASIC, RTL Design, Verilog, System Verilog, SoC, AMBA, Linting, Synthesis, CDC, UVM