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Confirmed on the employer's own hiring board on Oct 22, 2026. First seen by Alion on Oct 22, 2026. Larsen & Toubro scores B on the Alion truth index.

Overview
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Larsen & Toubro is an Indian multinational conglomerate with businesses in engineering, construction, heavy manufacturing, technology services and financial services. It builds infrastructure, power, hydrocarbon and defence projects worldwide and owns technology subsidiaries such as LTIMindtree and L&T Technology Services. Founded in 1938, the company is headquartered in Mumbai, Maharashtra, India.

Role Summary

Support FPGA-based SoC prototyping and hardware emulation activities for next-generation semiconductor products. Contribute to RTL preparation, FPGA synthesis, implementation, emulation compilation, platform bring-up, validation, and debugging under the guidance of senior engineers.

Work with platforms such as HAPS and Synopsys ZeBu to support pre-silicon validation and hardware/software co-verification. Collaborate with Design Verification, RTL Design, Firmware, and Software teams to resolve implementation and functional issues while contributing to automation, infrastructure maintenance, and improvements in verification turnaround time.

Roles & Responsibilities

  • FPGA Prototyping and Emulation: Support FPGA prototyping and emulation workflows, including RTL preparation, synthesis, implementation, compilation, model bring-up, and validation.
  • Synthesis and Implementation: Execute FPGA synthesis, place-and-route (P&R), and bitfile generation. Analyze build reports and assist in resolving implementation issues.
  • Platform Bring-up: Support FPGA board setup, bitfile programming, JTAG connectivity, clock/reset configuration, and basic hardware validation.
  • Emulation Compilation: Assist with emulator compilation, model configuration, and bring-up on platforms such as Synopsys ZeBu, following established workflows.
  • Timing and Resource Analysis: Analyze timing reports, FPGA resource utilization, and implementation results to identify bottlenecks and support optimization activities.
  • Interface and Connectivity Validation: Validate basic connectivity and functionality of interfaces such as SPI, I2C, UART, GPIO, MDIO, Ethernet, and other SoC peripherals, as applicable.
  • Debug and Issue Resolution: Perform initial debugging of compilation, connectivity, timing, and runtime issues using logs, waveform viewers, and available FPGA debug tools. Escalate complex issues to senior engineers.
  • Hardware/Software Co-verification: Support firmware execution and system-level validation on FPGA prototypes and emulators, including boot, memory access, register programming, and peripheral functionality.
  • Regression and Validation: Execute assigned tests, monitor regression results, analyze failures, and maintain validation status and issue-tracking records.
  • Automation and Productivity: Develop basic scripts using Python, Tcl, Perl, or Shell to automate build execution, log analysis, report generation, and repetitive engineering tasks.
  • Cross-functional Collaboration: Work with RTL Design, Design Verification, Firmware, Software, and senior Emulation engineers to support integration, debugging, and prototype readiness.
  • Documentation and Reporting: Maintain build logs, configuration details, validation results, debug notes, and setup documentation. Communicate progress, blockers, and technical issues to the team.
  • Methodology and Skill Development: Follow established engineering flows and contribute to process improvements while developing expertise in FPGA implementation, emulation, timing analysis, and system-level debugging.
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