{"id":3163801,"url":"https://alion.io/job/larsen-toubro-senior-lead-engineer-verification","title":"Senior Lead Engineer - Verification","company":{"id":2124,"name":"Larsen & Toubro","domain":"larsentoubro.com","url":"https://alion.io/company/larsentoubro","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":24,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":25,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-23T16:47:19Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-11-01T07:14:23Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Role\nL&T Semiconductor Technologies (LTSCT) is seeking an experienced and highly motivated Senior Lead Engineer, Verification to play a key technical leadership role in the development of next-generation semiconductor products.\nThis position provides an excellent opportunity to build a strong technical career while working on complex, state-of-the-art SoCs and IPs. As a Sr Lead Engineer, you will be responsible for driving verification strategy across IP, Subsystem, and SoC levels, leading verification architecture, mentoring engineers, and establishing reusable methodologies that improve quality and engineering productivity.\nYou will collaborate closely with System Architects, RTL Designers, Physical Design, Analog/Mixed-Signal, Post-Silicon Validation, Firmware, and Software teams throughout the product development lifecycle. You will actively participate in architecture reviews, influence design decisions from a verification perspective, and define scalable verification methodologies that enable first-silicon success.\nYour responsibilities will include defining verification strategies, creating reusable SystemVerilog/UVM-based verification environments, developing comprehensive verification plans, selecting verification tools and methodologies, driving functional and code coverage closure, and ensuring timely project execution with the highest quality standards.\nKey Responsibilities\nAs a Sr Lead Engineer, you will independently lead complex verification activities or provide technical leadership to a team responsible for IP, Subsystem, and SoC verification.\nTechnical Leadership\nProvide technical leadership for verification projects from architecture definition through verification signoff.\nOperate with a strong product and system-level mindset, understanding complete data flows and system interactions.\nDrive verification strategy based on product requirements and architecture specifications.\nDefine scalable and reusable Testbench (TB) architectures for multiple projects.\nServe as the Lead Verification Architect for reusable verification environments across product lines.\nParticipate in architecture, micro-architecture, design reviews, and technical decision-making.\nVerification Methodology\nDevelop reusable verification environments using SystemVerilog and UVM methodologies.\nCreate comprehensive Verification Plans, Test Plans, Functional Coverage Plans, Assertions, and Verification Closure Metrics.\nDesign and develop reusable Verification IPs (VIPs), Bus Functional Models (BFMs), scoreboards, checkers, monitors, and protocol-specific verification components.\nIntegrate and validate internally developed VIPs with third-party commercial VIP solutions.\nDrive constrained-random verification, coverage-driven verification, assertion-based verification, and formal verification where applicable.\nPerform environment benchmarking, profiling, optimization, and performance tuning.\nVerification Execution\nPlan and execute verification activities from block-level through full-chip verification.\nDevelop and execute regression strategies for functional, performance, and corner-case validation.\nAnalyze regression results, debug complex failures, identify root causes, and drive timely closure.\nDrive functional, code, assertion, toggle, and FSM coverage closure to meet verification signoff goals.\nEnsure compliance with project quality metrics and verification signoff criteria.\nTeam Leadership\nLead and mentor verification engineers across multiple projects.\nAllocate work based on technical complexity, project priorities, and individual strengths.\nConduct design reviews, code reviews, verification reviews, and technical audits.\nGuide engineers in debugging complex verification issues and adopting industry best practices.\nFoster a culture of technical excellence, innovation, collaboration, and continuous learning.\nCross-Functional Collaboration\nWork closely with RTL Design, System Architecture, Analog/Mixed-Signal Design, Physical Design, DFT, Firmware, Software, FPGA Prototyping, Emulation, and Post-Silicon Validation teams.\nCollaborate effectively with globally distributed engineering teams across multiple geographic locations.\nInterface directly with customers to understand technical requirements, provide engineering solutions, and resolve critical issues with urgency.\nMethodology & Productivity Improvement\nDrive continuous improvements in verification methodologies, engineering processes, and development flows.\nEvaluate, benchmark, and recommend EDA tools, simulators, emulators, formal verification tools, and verification technologies.\nWork closely with EDA vendors to establish efficient verification flows and deployment strategies.\nDevelop automation frameworks, regression infrastructure, verification dashboards, and productivity-enhancing solutions.\nBuild automation using scripting languages such as Python, Perl, Shell, or Tcl to improve verification efficiency.\nDocumentation & Knowledge Sharing\nPrepare verification architecture documents, user guides, methodology documentation, coding guidelines, and verification flow documentation.\nMaintain reusable verification assets and best-practice documentation.\nConduct technical seminars, design reviews, methodology workshops, knowledge-sharing sessions, and internal training programs.\nMentor junior engineers and support their technical and professional growth","description_format":"text","description_chars":5387,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous 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