{"id":1364772,"url":"https://alion.io/job/lattice-semiconductor-design-engineer-modeling","title":"Design Engineer - Modeling","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":4,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-09-30T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Manila, Philippines"],"countries":["PH"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17000,"max_usd":49000,"period":"year","method":null,"sample_n":2549},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"closed","first_seen_at":"2026-09-08T00:00:00Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-09-29T16:46:43Z","board_verified":false,"closed_at":"2026-09-29T16:46:43Z","days_open":21,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":21},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nSummary:\nThe Senior Design Engineer - Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers. The role translates IP specifications and hardware design intent into accurate, efficient, and maintainable models, while ensuring consistency with custom, analog, or digital implementations.\nThe engineer also drives validation, automation, and methodology improvements that strengthen model quality, scalability, and delivery efficiency across multiple projects. The position requires close collaboration with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams.\nKey Responsibilities\nDevelop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.\nTranslate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.\nPerform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.\nLead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.\nInvestigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.\nDevelop scripts and reusable workflows that improve model generation, validation, audit, release, traceability, and reporting.\nPartner with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, quality expectations, and delivery schedules.\nLead technical reviews, provide sound engineering direction, mentor less-experienced engineers, and promote consistent modeling and verification practices.\nIdentify quality or process gaps and drive practical improvements that reduce manual effort, improve scalability, and shorten turnaround time.\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\nDemonstrated senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification environments.\nStrong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.\nProficiency in Verilog and/or SystemVerilog for functional or behavioral modeling and simulation.\nWorking knowledge of semiconductor and integrated-circuit principles, including the effects of device behavior, layout, timing, power, and signal integrity on system behavior.\nExperience with digital simulation tools and familiarity with SPICE-type simulation, device models, or transistor-level design concepts.\nExperience with scripting or programming languages such as Python, Perl, TCL, or Shell for engineering automation.\nAbility to develop verification plans, define measurable completion criteria, analyze results, and drive technical issues to closure.\nStrong collaboration and teamwork skills, with openness to working across multi-site and cross-functional teams\nGood written and verbal communication skills, with the ability to ask clear questions, explain technical ideas, and learn from feedback\nundefined\nPreferred Qualifications\nExperience developing models that represent custom digital or analog IP behavior.\nExperience with timing, power, IBIS, signal-integrity, configuration, XML, or other metadata-based IP deliverables.\nExperience with model equivalency, regression automation, lint, CDC, or structured design-quality audits.\nFamiliarity with FPGA development platforms and integrated hardware-software enablement flows.\nExperience improving engineering processes, creating reusable methods, or deploying automation across multiple projects.\nExperience mentoring engineers or providing technical leadership within a project team.\nGenAI-Enabled Engineering Mindset\nUses approved GenAI tools responsibly to support learning, code review, debugging, documentation, automation, and technical summarization.\nProactively considers where GenAI can reduce repetitive work or improve quality, while independently verifying outputs and applying sound engineering judgment.\nProtects confidential and proprietary information and follows applicable company policies when using AI-assisted tools.\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.","description_format":"text","description_chars":6565,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Hardware","Smart City"],"lifecycle":[{"event":"open","at":"2026-09-28T01:41:50Z"},{"event":"close","at":"2026-09-29T16:46:43Z"}],"liveness":null,"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-design-engineer-modeling","json_url":"https://alion.io/job/lattice-semiconductor-design-engineer-modeling.json","meta":{"generated_at":"2026-10-01T04:55:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4487,"day_limit":5000,"remaining_today":513,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}