{"id":3496909,"url":"https://alion.io/job/lattice-semiconductor-principal-engineer-architecture-usb-systems-ip","title":"Principal Engineer, Architecture (USB Systems & IP)","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":7,"ghost_share":0,"stale_share":0.429,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States","Hillsboro, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":118000,"max_usd":239000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1961},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"RTOS","optional":false},{"name":"Linux","optional":true},{"name":"Windows","optional":true}],"status":"live","first_seen_at":"2026-10-29T00:00:00Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-11-01T05:33:06Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nOverview\nLattice Semiconductor is seeking an experienced and highly motivated Principal Engineer to join our Architecture team. In this role, you will serve as a technical leader defining next-generation USB solutions across FPGA, SoC FPGA, and system platforms. You will work closely with architecture, silicon design, software, applications, product planning, and ecosystem partners to develop innovative USB-based solutions that enable differentiated customer experiences.\nThe ideal candidate combines deep USB protocol expertise with hands-on experience developing USB devices, embedded firmware, software stacks, and USB controller architectures. This role requires both technical leadership and strong cross-functional collaboration skills, with the ability to influence product strategy and drive complex architectural initiatives from concept through deployment.\nResponsibilities\nDefine architecture and technical requirements for future USB subsystem solutions across FPGA and SoC product families.\nServe as the company-wide subject matter expert for USB technologies including USB 2.0, USB 3.x, USB Type-C, USB Power Delivery (PD), and related ecosystem standards.\nEvaluate, select, and guide integration of third-party USB controller, PHY, and protocol IP solutions.\nDrive architecture studies, competitive analysis, and technology assessments related to USB connectivity, embedded systems, and customer applications.\nCollaborate with silicon design teams to define USB subsystem architectures, performance targets, configurability, and integration requirements.\nWork closely with firmware and software teams to define reference platforms, software architecture, and production-ready solutions.\nPartner with applications engineering and strategic customers to understand emerging requirements and translate them into product roadmap recommendations.\nDevelop technical specifications, architectural proposals, white papers, and executive-level presentations.\nContribute to system-level validation, interoperability testing, and compliance strategies.\nMentor engineers across multiple disciplines and provide technical guidance on complex USB-related challenges.\nEngage with standards organizations, ecosystem partners, and industry forums as required to support technology strategy.\nRequired Qualifications\nM.S. or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\n12+ years of industry experience in semiconductor, embedded systems, FPGA, ASIC, or SoC development.\nDemonstrated technical leadership experience at the subsystem or system architecture level.\nDeep understanding of USB protocols and architectures, including:USB 2.0\nUSB 3.x SuperSpeed\nUSB Type-C\nUSB Power Delivery (PD)\nUSB hubs and bridges\nDevice, host, and OTG implementations\n\nHands-on experience developing USB-based applications and products.\nExperience implementing or integrating USB device, host, or dual-role solutions.\nStrong understanding of the USB controller IP ecosystem, including:Host controllers\nDevice controllers\nDual-role controllers\nUSB PHY architectures\nDMA and data movement architectures\nIndustry-standard third-party USB IP offerings\n\nExperience developing embedded firmware for USB-based systems and applications.\nExperience with USB boot loaders, firmware update mechanisms, device management, and enumeration flows.\nExperience developing reference software, middleware, BSPs, or USB application frameworks.\nExperience with USB application driver development, device drivers, kernel-level software, or system software integration.\nStrong understanding of embedded processors, RTOS environments, and firmware/software partitioning.\nExperience debugging complex HW/FW/SW interactions using protocol analyzers, logic analyzers, and software debugging tools.\nDemonstrated ability to lead technical discussions across architecture, design, software, validation, and product organizations.\nExcellent written and verbal communication skills.\nPreferred Qualifications\nFamiliarity with FPGA architectures and FPGA-based USB implementations.\nExperience with Linux USB subsystems, driver frameworks, and kernel development.\nExperience with Windows USB driver development and device certification processes.\nKnowledge of PCIe, Ethernet, MIPI, UART, SPI, I2C, or other common embedded interfaces.\nExperience with USB compliance testing and certification.\nExperience evaluating make-versus-buy decisions for third-party IP and ecosystem software.\nUnderstanding of security concepts including secure boot, device authentication, firmware integrity, and trusted update mechanisms.\nExperience working directly with strategic customers and ecosystem partners.\nPrior participation in standards development organizations or industry consortiums.\nLeadership Expectations\nAs a Principal Engineer, you will be expected to:\nProvide technical leadership across multiple product generations.\nInfluence product and technology strategy through data-driven architectural analysis.\nMentor engineers and foster engineering excellence across the organization.\nDrive consensus among diverse stakeholders while maintaining focus on customer value and product differentiation.\nIndependently lead complex initiatives with minimal supervision.\nIdentify emerging technology trends and recommend strategic investments aligned with company objectives.\nPay & Benefits\nConsistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.\nFor candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.\nBase Pay Range\n245,000.00In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.\nLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.\nAs an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.","description_format":"text","description_chars":8865,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Retirement plans"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-30T01:45:01Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6 · green card filings: 5","filings_12m":6,"filings_prev_12m":9,"green_card_filings_12m":5,"median_offered_wage_usd":174318,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":44,"reasons":["conf:0","velocity","win:early","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-principal-engineer-architecture-usb-systems-ip","json_url":"https://alion.io/job/lattice-semiconductor-principal-engineer-architecture-usb-systems-ip.json","meta":{"generated_at":"2026-11-01T14:02:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":21629,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1792396},"rest":"https://alion.io/mcp/rest/get_company?id=1792396"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flattice-semiconductor-principal-engineer-architecture-usb-systems-ip"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flattice-semiconductor-principal-engineer-architecture-usb-systems-ip"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flattice-semiconductor-principal-engineer-architecture-usb-systems-ip"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lattice-semiconductor-principal-engineer-architecture-usb-systems-ip\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flattice-semiconductor-principal-engineer-architecture-usb-systems-ip"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3496909}},{"tool":"search_jobs","arguments":{"company":"latticesemi.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3496909},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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