{"id":3508982,"url":"https://alion.io/job/lattice-semiconductor-senior-design-engineer-modeling","title":"Senior Design Engineer - Modeling","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":92,"open_postings":9,"ghost_share":0,"stale_share":0.333,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Manila, Philippines"],"countries":["PH"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":45000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-30T06:35:36Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-11-04T07:52:06Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nThis position for Senior Design Engineer - Modeling builds and runs the stand-alone testbenches, tests, regressions, and equivalence flows that independently validate the behavioral, functional, and architectural models and related collateral delivered by the Design Modeling team. The role ensures that delivered models, especially those used for user and software simulations, are functionally correct and equivalent to the actual hardware design.\nThe engineer works as part of the new Unit Testing team under the direction of the Design Modeling Manager and the Staff Design Engineer, and collaborates closely with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams. The position supports validation of HLM, XML, and generated Chip Builder artifacts, enabling the senior modeling engineers to remain focused on customer commitments and delivery.\nKey Responsibilities\nDevelop stand-alone testbenches, directed and constrained-random tests, checkers, and scoreboards, in UVM or non-UVM format, to verify that functional and behavioral models match the actual hardware design.\nBuild regression suites, coverage collection, and coverage dashboards, and support release qualification of HLM, IP XML, and generated Chip Builder artifacts against measurable release-exit criteria.\nAuthor, maintain, and execute test plans for assigned behavioral, functional, and architectural models, tracing each feature and behavior to tests and coverage points.\nExecute formal equivalency runs using Conformal XL or other industry tools for assigned custom IPs, covering cell behavioralized model versus schematic, and custom IP functional model versus full IP schematic. Set up mappings and constraints and debug non-equivalent points to root cause.\nDetect and triage RTL-model, schematic-model, primitive, XML, and configuration mismatches early in the development cycle, and work with model owners and design owners to drive them to closure.\nInvestigate and resolve model behavior, hardware-to-software integration, and customer-facing issues escaping into delivery, and feed lessons learned back into tests and coverage.\nDevelop scripts and reusable workflows that improve test generation, regression, audit, traceability, and reporting.\nReport test status, coverage, equivalence results, and open issues in the team reporting cadence, and document assumptions and limitations.\nProvide technical guidance, participate in technical reviews, and promote consistent verification practices across the Design Modeling team.\nRequired Qualifications:\nBachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\nDemonstrated senior-level experience (typically 5 or more years) in digital, custom, analog, FPGA, ASIC, or IP verification, validation, or modeling environments.\nStrong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.\nProficiency in Verilog and SystemVerilog, with working knowledge of UVM and stand-alone (non-UVM) testbench techniques.\nExperience with digital simulation tools (such as Xcelium, VCS, or Questa) and familiarity with SPICE-type simulation, device models, or schematic and transistor-level design concepts.\nWorking knowledge of formal equivalence checking concepts and tools.\nExperience with scripting or programming languages such as Python, Perl, TCL, or Shell for regression and flow automation.\nAbility to develop test plans, define measurable completion criteria, analyze results, and drive technical issues to closure.\nStrong collaboration and teamwork skills, with openness to working across multi-site and cross-functional teams.\nGood written and verbal communication skills, with the ability to ask clear questions, explain technical ideas, and learn from feedback.\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nPhilippinesLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.","description_format":"text","description_chars":5910,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-30T06:35:36Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":4,"expected_fill_days":44,"reasons":["conf:10","velocity","win:early","comp:brand"],"computed_at":"2026-11-04T06:34:25Z"},"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-senior-design-engineer-modeling","json_url":"https://alion.io/job/lattice-semiconductor-senior-design-engineer-modeling.json","meta":{"generated_at":"2026-11-04T21:17:06Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":32964,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-05T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1792396},"rest":"https://alion.io/mcp/rest/get_company?id=1792396"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flattice-semiconductor-senior-design-engineer-modeling"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flattice-semiconductor-senior-design-engineer-modeling"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flattice-semiconductor-senior-design-engineer-modeling"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lattice-semiconductor-senior-design-engineer-modeling\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flattice-semiconductor-senior-design-engineer-modeling"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3508982}},{"tool":"search_jobs","arguments":{"company":"latticesemi.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3508982},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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