{"id":2838412,"url":"https://alion.io/job/lattice-semiconductor-senior-staff-design-engineer-2","title":"Senior Staff Design Engineer","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":79,"open_postings":6,"ghost_share":0,"stale_share":0.833,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":43000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1625},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-08-28T00:00:00Z","employer_posted_date":"2026-08-28","last_verified_at":"2026-10-25T16:31:51Z","board_verified":true,"closed_at":null,"days_open":58,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":58},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nJoin the winning team! Lattice is looking for a motivated and experienced Senior Staff Engineer to lead the development, integration, and productization of high-performance interface solutions, including PCI Express (PCIe), Ethernet, USB, MIPI, SerDes, and related PHY technologies for next-generation FPGA products.\nThe successful candidate will bring a subsystem ownership mindset, with strong RTL expertise and the ability to drive technical decisions across protocol architecture, PHY and analog behavior, soft IP, software and firmware enablement, package and platform integration, validation, interoperability, and customer deployment. The role works closely with hardware, analog and mixed-signal, software, validation, applications, product engineering, and external IP partners.\nKey Responsibilities:\nLead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interface subsystems.\n\nOwn subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.\n\nDrive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.\n\nWork with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.\n\nDrive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP. Define requirements, evaluate deliverables, resolve integration and verification issues, and drive technical closure through product development and silicon bring-up.\n\nIdentify technical risks and dependencies, support milestone and release-readiness reviews, and communicate clear recommendations to stakeholders.\n\nMentor engineers and improve design, debug, review, and release methodologies across the team.\n\nRequired Qualifications:\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\n\n15+years of experience in ASIC, SoC, or FPGA design and product-development.\n\nStrong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.\n\nDeep expertise in at least one high-speed interface area such as PCIe, Ethernet, USB, MIPI, SerDes, or related PHY/controller technology.\n\nDemonstrated ability to understand an interface as a complete subsystem and drive dependencies beyond the RTL block.\n\nExperience applying AI-assisted tools and workflows to accelerate engineering productivity, technical investigation, data analysis, and documentation.\n\nExperience working with DFT and DFD methodologies, including scan, ATPG, debug observability, silicon bring-up, or production-test considerations.\n\nExperience working with Design Verification teams and using system simulation, emulation, or FPGA prototyping environments to validate end-to-end subsystem behavior and accelerate pre-silicon debug.\n\nExperience leading complex cross-functional debug and driving issues from initial investigation through verified closure.\n\nExperience with pre-silicon verification, silicon bring-up, laboratory debug, interoperability, or customer issue resolution.\n\nStrong technical communication, stakeholder alignment, and independent decision-making skills.\n\nPreferred Qualifications:\nExperience with more than one interface family, including connectivity or video protocols such as PCIe, Ethernet, USB, MIPI CSI-2/DSI, D-PHY/C-PHY, or SerDes.\n\nUnderstanding of PHY and mixed-signal behavior associated with high-speed interface IP, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up. Direct analog circuit design experience is not required.\n\nExperience working with third-party suppliers of digital controller, PHY, or mixed-signal IP to define requirements, assess deliverables, and resolve architecture, integration, verification, and silicon issues.\n\nFamiliarity or experience in Physical Design e.g.: Synthesis, LEC or Timing Closure.\n\nExperience in design quality checks methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.\n\nKnowledge of firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.\n\nExposure to package, board, platform, signal-integrity, compliance, and interoperability considerations for high-speed interfaces.\n\nExperience influencing architecture or methodology and mentoring engineers across organizational boundaries.\n\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.","description_format":"text","description_chars":6663,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-19T07:56:42Z"}],"visa":[],"liveness":{"score":26,"band":"fade","label":"Fading","p_open":0.9,"p_active":0.792,"p_room":0.36,"age_days":58,"expected_fill_days":34,"reasons":["conf:62","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-senior-staff-design-engineer-2","json_url":"https://alion.io/job/lattice-semiconductor-senior-staff-design-engineer-2.json","meta":{"generated_at":"2026-10-25T16:38:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24002,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1792396},"rest":"https://alion.io/mcp/rest/get_company?id=1792396"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flattice-semiconductor-senior-staff-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flattice-semiconductor-senior-staff-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flattice-semiconductor-senior-staff-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lattice-semiconductor-senior-staff-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flattice-semiconductor-senior-staff-design-engineer-2"}]}