{"id":1364751,"url":"https://alion.io/job/lattice-semiconductor-silicon-integration-design-engineer-timing-model","title":"Silicon Integration Design Engineer - Timing Model","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":5,"ghost_share":0,"stale_share":0.8,"repost_share":0,"time_to_fill_p50_days":33,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-09-15T00:00:00Z","employer_posted_date":"2026-09-15","last_verified_at":"2026-10-13T16:17:18Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nDetailed Description\nCollaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.\nUnderstand IP functionality to define timing arcs and constraints per spec and deliver to software team.\nPerform quality checks on timing models to confirm all timing arcs meet software requirements.\nAddress issues such as missing timing arcs and missing clock information.\nGenerate timing reference models based on IP requirements\nCompare timing models: Current proprietary format vs. Liberty format (.lib).\nHandle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.\nGenerate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.\nFPGA power model know-how and knowledge will be added advantage.\nExperience with PrimeTime/Liberate will be added advantage.\nAdditional Job Description\n10 yrs experience of hardware integration design\nFPGA timing model know-how and knowledge will be added advantage.\nSuccessfully went through whole development from start to Tape Out of at least 2 products.\nProficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.\nWorking knowledge of System Verilog, synthesis, and static timing analysis\nSpecialist in floor-planning, power estimate, timing and back-end methodologies\nExperience with Linux scripting and Python\nExperience and knowledge of PnR is a plus\nStrong written and oral communication skills\nThe ability to stay up-to-date with the latest advancements in technology & design\nAbility to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.\nDetailed Description\nCollaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.\nUnderstand IP functionality to define timing arcs and constraints per spec and deliver to software team.\nPerform quality checks on timing models to confirm all timing arcs meet software requirements.\nAddress issues such as missing timing arcs and missing clock information.\nGenerate timing reference models based on IP requirements\nCompare timing models: Current proprietary format vs. Liberty format (.lib).\nHandle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.\nGenerate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.\nFPGA power model know-how and knowledge will be added advantage.\nExperience with PrimeTime/Liberate will be added advantage.\nAdditional Job Description\n10 yrs experience of hardware integration design\nFPGA timing model know-how and knowledge will be added advantage.\nSuccessfully went through whole development from start to Tape Out of at least 2 products.\nProficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.\nWorking knowledge of System Verilog, synthesis, and static timing analysis\nSpecialist in floor-planning, power estimate, timing and back-end methodologies\nExperience with Linux scripting and Python\nExperience and knowledge of PnR is a plus\nStrong written and oral communication skills\nThe ability to stay up-to-date with the latest advancements in technology & design\nAbility to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.","description_format":"text","description_chars":5470,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Hardware","Smart City"],"lifecycle":[{"event":"open","at":"2026-09-28T01:41:50Z"}],"visa":[],"liveness":{"score":65,"band":"ok","label":"Likely open","p_open":1,"p_active":0.861,"p_room":0.75,"age_days":28,"expected_fill_days":33,"reasons":["conf:11","velocity","win:late","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-silicon-integration-design-engineer-timing-model","json_url":"https://alion.io/job/lattice-semiconductor-silicon-integration-design-engineer-timing-model.json","meta":{"generated_at":"2026-10-14T02:35:06Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3945,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1792396},"rest":"https://alion.io/mcp/rest/get_company?id=1792396"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flattice-semiconductor-silicon-integration-design-engineer-timing-model"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flattice-semiconductor-silicon-integration-design-engineer-timing-model"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flattice-semiconductor-silicon-integration-design-engineer-timing-model"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lattice-semiconductor-silicon-integration-design-engineer-timing-model\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flattice-semiconductor-silicon-integration-design-engineer-timing-model"}]}