{"id":3859707,"url":"https://alion.io/job/lattice-semiconductor-staff-design-engineer-2","title":"Staff Design Engineer","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":94,"open_postings":12,"ghost_share":0,"stale_share":0.25,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-11-06T08:44:49Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-09T19:10:26Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nPosition Summary\nJoin the winning team! Lattice is looking for a motivated and experienced Staff Design Engineer to integrate and productize USB IP and subsystems for next-generation FPGA products. The role focuses on USB 2.0 and USB 3.x controller and PHY integration, spanning subsystem validation, software enablement, silicon bring-up, and collaboration across Design, DV, Software, Applications, and external IP partners.\nKey Responsibilities\nOwn the integration of USB controller and USB PHY IP into the FPGA subsystem, including digital interfaces, configuration paths, clock/reset connectivity, and integration requirements.\n Define and implement the subsystem-level RTL, wrappers, adapters, control logic, and configuration interfaces required to integrate USB controller and PHY IP.\nWork with Design Verification teams to define integration test plans and validate end-to-end USB subsystem behavior through simulation, emulation, FPGA prototyping, coverage closure, and pre-silicon debug.\nDrive subsystem-level root-cause analysis across USB controller-to-PHY interaction, integration RTL, software or firmware configuration, interoperability, compliance, and silicon behavior.\nWork with software and firmware teams to define and validate USB configuration, feature enablement, diagnostics, enumeration, initialization, and user-flow requirements.\nIntegrate and review DFT and DFD requirements for the USB subsystem, including testability, debug observability, silicon bring-up, and production-test considerations.\nWork with third-party suppliers of USB controller and PHY IP to clarify interface and configuration requirements, review deliverables, and resolve integration, verification, and silicon issues.\nDevelop and maintain USB subsystem integration specifications, interface requirements, configuration documentation, and bring-up guidelines. \nSupport integrated USB subsystem bring-up, laboratory debug, protocol analysis, compliance and interoperability testing, and customer issue resolution; document findings and drive assigned issues to closure.\nIdentify engineering activities that can benefit from AI assistance, and propose, develop, and deploy practical AI-assisted workflows for design, verification, debug, data analysis, and technical documentation.\nParticipate in design reviews and quality checks, and contribute to continuous improvement of design and debug methodologies.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\nTypically 8+ years of semiconductor, ASIC, SoC, or FPGA design experience.\nStrong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.\nStrong experience with USB 2.0 or USB 3.x controller, protocol, subsystem integration, or related USB PHY technology.\nExperience working with Design Verification teams and debugging pre-silicon design or integration issues using simulation, emulation, or FPGA prototyping environments.\nExperience supporting silicon bring-up, laboratory debug, interoperability, or customer issue resolution.\nExperience working with DFT or DFD methodologies, including testability, debug observability, scan/ATPG, silicon bring-up, or production-test considerations.\nDemonstrated experience identifying opportunities, proposing, developing, and implementing AI-assisted engineering workflows to improve design and integration productivity, technical investigation, debug, data analysis, and documentation.\nStrong technical communication and collaboration skills across engineering disciplines.\nPreferred Qualifications\nExperience with USB protocol operation and debug, including enumeration, link state transitions, power management, error recovery, and compliance or interoperability testing.\nExperience with USB controller-to-PHY interfaces and specifications, such as UTMI/UTMI+, ULPI, PIPE, or related integration interfaces. \nExperience with SerDes-based protocols or high-speed serial interfaces, including protocol architecture, controller-to-PHY integration, link bring-up, or system-level debug.\nUnderstanding of USB PHY and mixed-signal behavior, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up. Direct analog circuit design experience is not required.\nExperience integrating third-party USB controller or PHY IP and working with external IP suppliers on requirements, deliverables, integration, verification, or silicon issues.\nFamiliarity with physical-design interfaces such as synthesis, LEC, static timing analysis, or timing closure.\nExperience with design-quality methodologies such as Lint, CDC, RDC, low-power/UPF, or related structural checks.\nKnowledge of firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.\nExposure to USB compliance, interoperability, package, board, signal-integrity, connector, or platform-level considerations.\n#LI-DNP\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nMalaysiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.","description_format":"text","description_chars":7106,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-11-06T08:44:49Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":44,"reasons":["conf:1","velocity","win:early","comp:brand"],"computed_at":"2026-11-09T06:03:00Z"},"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-staff-design-engineer-2","json_url":"https://alion.io/job/lattice-semiconductor-staff-design-engineer-2.json","meta":{"generated_at":"2026-11-09T22:16:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11643,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1792396},"rest":"https://alion.io/mcp/rest/get_company?id=1792396"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flattice-semiconductor-staff-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flattice-semiconductor-staff-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flattice-semiconductor-staff-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lattice-semiconductor-staff-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flattice-semiconductor-staff-design-engineer-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3859707}},{"tool":"search_jobs","arguments":{"company":"latticesemi.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3859707},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}