{"id":3306967,"url":"https://alion.io/job/lattice-semiconductor-staff-eda-engineer","title":"Staff EDA Engineer","company":{"id":1792396,"name":"Lattice Semiconductor","domain":"latticesemi.com","url":"https://alion.io/company/latticesemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":7,"ghost_share":0,"stale_share":0.429,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":58000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Cadence Tempus","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-10-26T00:00:00Z","employer_posted_date":"2026-10-26","last_verified_at":"2026-10-30T06:35:36Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Lattice Overview\nThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.\nEnergy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.\nJob Description:\nLattice is seeking a Senior CAD/EDA Engineer with deep expertise in Static Timing Analysis (STA), Place and Route (PNR), and hierarchical timing abstraction using Extracted Timing Models (ETM) and Quick Timing Models (QTM), to join our CAD/EDA Engineering group in Pune, India. Qualified candidates must hold a BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience on 5, 7, 16, or 28 nm process technology nodes. This individual will be a key driver in developing, deploying, and supporting the logic and digital design implementation and signoff methodologies and flows across the company's FPGA product lines\nThe candidate's general responsibilities include the following:\nStatic Timing Analysis and Signoff\nOwn and maintain the multi-corner multi-mode (MCMM) STA signoff methodology, including constraint development, timing closure criteria, and signoff sign-check automation.\nDevelop and support timing signoff flows using Synopsys PrimeTime, PrimeTime SI, and Cadence Tempus, covering setup, hold, recovery/removal, and transition/capacitance checks.\nDeploy advanced variation modeling methodologies including AOCV, POCV, and LVF, and define derating and margining strategies across process nodes.\nDrive crosstalk and signal integrity analysis, noise-aware timing, and correlation between implementation and signoff timing engines.\nDefine and automate SDC generation, validation, and equivalence checking across RTL, synthesis, PNR, and signoff stages.\nTiming Abstraction: ETM and QTM\nOwn the hierarchical timing model generation methodology, including ETM extraction for hardened blocks and IP, and QTM construction for blocks that are not yet implemented.\nDefine model validation and correlation procedures that quantify ETM/QTM accuracy against flat and full block timing, and establish acceptance criteria for model release.\nDevelop automation for context-aware and mode-aware model generation, interface logic model (ILM) alternatives, and model regeneration triggered by block-level ECOs.\nDrive top-level timing closure strategies that rely on abstracted models to reduce runtime and memory footprint on large hierarchical designs.\nEstablish guidance for design teams on when to apply ETM, QTM, ILM, or flat analysis, and document the accuracy and runtime trade-offs of each.\nPhysical Implementation and Place and Route\nDevelop and support physical design place and route and tape-out flows for advanced FinFET nodes (28nm, 16nm, 7 nm and below) using Cadence Innovus and/or Synopsys IC Compiler II and Fusion Compiler.\nDrive floorplanning, power planning, placement, clock tree synthesis, and routing methodology, including low-skew and clock mesh structures.\nOwn post-CTS and post-route tool ECO flows, timing and DRV closure automation, and physical-aware ECO implementation.\nSupport early IR drop and power analysis, EM/IR signoff hooks, and congestion and routability analysis within the implementation flow.\nSupport IP block and full-chip integration for designs on 5, 7, 16, and 28 nm process nodes.\nMethodology, Automation, and Support\nCreate, release, and maintain design scripts and utilities that automate EDA tool flows across physical design, timing signoff, and QA.\nDefine and implement comprehensive design QA procedures and regression test suites for the backend PNR and STA flows.\nTrack and resolve tool and technology file issues through hands-on, objective-driven engagement with foundry and EDA vendor support teams.\nDrive cross-functional initiatives and design methodology alignment across geographically distributed design and CAD/EDA teams.\nDocument and deliver training on developed methodology and EDA flows to the broader engineering organization.\nMonitor EDA industry trends and new tool capabilities by attending conferences and research forums and evaluate their applicability to Lattice flows.\nMentor junior CAD engineers and serve as an escalation point for complex timing and physical design issues.\nAdditional Information:\nThis position requires a successful background and reference checks and satisfactory proof of your right to work in:\nIndiaLattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.\nLattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.","description_format":"text","description_chars":6015,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips"],"lifecycle":[{"event":"open","at":"2026-10-27T01:48:26Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":4,"expected_fill_days":44,"reasons":["conf:4","velocity","win:early","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/lattice-semiconductor-staff-eda-engineer","json_url":"https://alion.io/job/lattice-semiconductor-staff-eda-engineer.json","meta":{"generated_at":"2026-10-30T09:15:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13304,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1792396},"rest":"https://alion.io/mcp/rest/get_company?id=1792396"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Flattice-semiconductor-staff-eda-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Flattice-semiconductor-staff-eda-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Flattice-semiconductor-staff-eda-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/lattice-semiconductor-staff-eda-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Flattice-semiconductor-staff-eda-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3306967}},{"tool":"search_jobs","arguments":{"company":"latticesemi.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3306967},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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