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level HS session and using Top context from SoC for Block-SoC Interface timing closure.\n\n- Generating timing ECO using Tweaker/PrimeClosure.\n\nRequirement : \n\n- 5+ years of experience in timing closure of high frequency blocks (> GHz range).\n\n- Analyzing the timing reports and identifying both design and constraints related issues.\n\n- Worked on blocks with multiple power and voltage domains.\n\n- Preferred EDA tool experience : Primetime, Tweaker/PrimeClosure, Innovus.\n\n- Strong Understanding of DFT modes requirements for timing signoff.\n\n- Good understanding of physical design flow and ECO implementation.\n\n- Strong understanding of SDC constraints, OCV, AOCV, POCV analysis.\n\n- Strong TCL/scripting knowledge is mandatory.\nSkills\nStatic Timing Analysis, SoC, DFT, EDA, Primetime, High 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