{"id":4028423,"url":"https://alion.io/job/leadsoc-technologies-lead-design-verification-engineer","title":"Lead Design Verification Engineer","company":{"id":3809842,"name":"LeadSoc Technologies","domain":"leadsoc.com","url":"https://alion.io/company/leadsoc-technologies-india","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Synopsys VCS","optional":true}],"status":"live","first_seen_at":"2026-11-10T17:35:30Z","employer_posted_date":null,"last_verified_at":"2026-11-10T17:35:30Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"We are looking for a technically strong Lead Design Verification Engineer with extensive hands-on experience in IP/SoC verification, SystemVerilog, UVM and PCIe protocols (Gen5/Gen6/Gen7). The ideal candidate should have strong expertise in developing scalable verification environments, building robust testbenches and driving complex protocol-level verification from specification to signoff.\n\nKey Responsibilities:\nLead hands-on design verification of complex PCIe IP/SoC blocks across Gen5, Gen6 and Gen7.\nDevelop and maintain reusable, scalable UVM-based verification environments.\nArchitect and implement SystemVerilog-based testbenches, agents, sequences, drivers, monitors and scoreboards.\nDevelop constrained-random, directed and coverage-driven verification strategies.\nVerify PCIe protocol features, transaction handling, link training, configuration, power management and error handling.\nDrive functional coverage, code coverage and verification closure.\nDebug complex RTL and simulation failures through waveform analysis and root-cause investigation.\nCollaborate closely with RTL, Architecture and System teams to resolve design and verification issues.\nDrive verification planning, execution, regression management and signoff.\n\nMandatory Technical Skills:\n6-12 years of hands-on experience in ASIC/SoC Design Verification.\nStrong expertise in SystemVerilog and UVM.\nExtensive experience in developing and debugging complex UVM testbenches.\nStrong hands-on verification experience in PCIe Gen5 / Gen6 / Gen7.\nGood understanding of PCIe protocol architecture, transaction and data link layers, LTSSM and link training.\nExpertise in constrained-random verification, assertions (SVA), functional coverage and coverage closure.\nStrong debugging skills with simulation and waveform analysis tools.\nProficiency in scripting languages such as Python, Perl or Tcl.\n\nPreferred Skills:\nExperience in PCIe Controller, PHY or Subsystem verification.\nExposure to PCIe compliance, protocol corner cases and error injection.\nKnowledge of AXI, CXL, NVMe or other high-speed interface protocols.\nExperience with Synopsys VCS, Cadence Xcelium or Siemens Questa.\nSkills\nPCIE, SystemVerilog, UVM","description_format":"text","description_chars":2190,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-10T17:35:30Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":29,"reasons":["seen:0","win:early"],"computed_at":"2026-11-11T01:21:14Z"},"pay":null,"html_url":"https://alion.io/job/leadsoc-technologies-lead-design-verification-engineer","json_url":"https://alion.io/job/leadsoc-technologies-lead-design-verification-engineer.json","meta":{"generated_at":"2026-11-11T01:21:14Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":612,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3809842},"rest":"https://alion.io/mcp/rest/get_company?id=3809842"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fleadsoc-technologies-lead-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fleadsoc-technologies-lead-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fleadsoc-technologies-lead-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/leadsoc-technologies-lead-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fleadsoc-technologies-lead-design-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4028423}},{"tool":"search_jobs","arguments":{"company":"leadsoc.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4028423},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}