{"id":3994499,"url":"https://alion.io/job/leadsoc-technologies-lead-static-timing-analysis-sta-engineer","title":"Lead Static Timing Analysis (STA) Engineer","company":{"id":3809842,"name":"LeadSoc Technologies","domain":"leadsoc.com","url":"https://alion.io/company/leadsoc-technologies-india","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-11-10T00:36:15Z","employer_posted_date":null,"last_verified_at":"2026-11-10T00:36:15Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.\n\nKey Responsibilities:\nTiming Sign-off and Analysis\nTiming Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.\nConstraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).\nMMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).\nCritical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all setup and hold violations.\nSignal Integrity (SI) & Noise: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.\n\nMethodology and Flow:\nDevelop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.\nAutomate repetitive tasks and report generation using scripting languages.\nGenerate final timing reports and sign-off collateral for tape-out.\n\nEducation:\n\nBachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.\n\nTechnical Skills:\n\nEDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, PrimeTime), Cadence (e.g., Innovus), or Mentor Graphics.\nSkills\nMMMC, Multi-Mode Multi-Corner, SDC, STA, Static Timing Analysis, Synopsys Design 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