{"id":3994498,"url":"https://alion.io/job/leadsoc-technologies-senior-layout-design-engineer","title":"Senior Layout Design Engineer","company":{"id":3809842,"name":"LeadSoc Technologies","domain":"leadsoc.com","url":"https://alion.io/company/leadsoc-technologies-india","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false}],"status":"live","first_seen_at":"2026-11-10T00:36:15Z","employer_posted_date":null,"last_verified_at":"2026-11-10T00:36:15Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"We are looking for an experienced Analog Layout Design Engineer with hands-on expertise in eFuse macro layout and a strong understanding of SRAM layout design. The ideal candidate should have solid fundamentals in full-custom IC layout, physical verification and transistor-level layout implementation.\n\nKey Responsibilities:\nDevelop and implement full-custom eFuse macro layouts.\nPerform transistor-level layout, placement and routing of eFuse circuits.\nWork on SRAM layout blocks with an understanding of bitcells and memory peripheral circuits.\nExecute physical verification activities, including DRC, LVS and ERC.\nPerform layout debugging, optimization and physical verification closure.\nCollaborate with circuit design and memory design teams to ensure layout meets design specifications.\nFollow technology-specific layout rules and reliability guidelines.\n\nRequired Skills:\n3-7 years of hands-on experience in Custom IC / Analog Layout.\nDirect experience in eFuse macro layout design.\nGood understanding of SRAM layout design and memory architecture.\nStrong knowledge of transistor-level layout and CMOS fundamentals.\nHands-on experience with Cadence Virtuoso.\nGood understanding of DRC, LVS, ERC and parasitic extraction.\nExposure to advanced CMOS technology nodes and layout design methodologies.\n\nPreferred Skills:\nExposure to OTP / MTP / NVM layout.\nUnderstanding of SRAM bitcells, sense amplifiers and memory peripheral circuits.\nExperience with Mentor Graphics Calibre.\nExposure to FinFET technology nodes.\nSkills\nCadence, Layout, Virtuoso, eFuse","description_format":"text","description_chars":1558,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-10T00:36:15Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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