{"id":4010367,"url":"https://alion.io/job/leadsoc-technologies-staff-engineer-design-for-testability-dft","title":"Staff Engineer - Design for Testability (DFT)","company":{"id":3809842,"name":"LeadSoc Technologies","domain":"leadsoc.com","url":"https://alion.io/company/leadsoc-technologies-india","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys TestMAX","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-11-10T09:35:30Z","employer_posted_date":null,"last_verified_at":"2026-11-10T09:35:30Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"We are looking for a technically strong Staff Engineer - DFT with extensive hands-on experience in MBIST, ATPG and Scan Insertion for complex ASIC/SoC designs. The ideal candidate should have strong expertise in end-to-end DFT implementation, test architecture, coverage optimization and production test readiness.\n\nKey Responsibilities:\nDrive end-to-end DFT implementation for complex IP and SoC designs.\nDevelop and implement scan insertion strategies, including scan chain architecture, stitching and optimization.\nOwn MBIST architecture, memory test implementation and test coverage closure.\nDevelop and optimize ATPG patterns for stuck-at, transition delay and other fault models.\nDrive DFT rule checking (DRC), test coverage analysis and pattern validation.\nPerform scan compression, test point insertion and pattern optimization.\nDebug DFT-related issues and resolve coverage, timing and testability challenges.\nCollaborate with RTL, Physical Design, STA and Silicon Validation teams for DFT integration and signoff.\nSupport post-silicon bring-up, manufacturing test and production test readiness.\n\nMandatory Technical Skills:\n7-12 years of hands-on experience in ASIC/SoC DFT implementation.\nStrong expertise in MBIST, ATPG and Scan Insertion.\nSolid understanding of scan architecture, scan compression and test methodologies.\nHands-on experience with stuck-at, transition delay and fault coverage analysis.\nStrong knowledge of MBIST controllers, memory test algorithms and repair methodologies.\nExperience in DFT DRC, pattern generation, coverage analysis and debugging.\nProficiency in industry-standard DFT tools such as Synopsys TestMAX / TetraMAX, Mentor Tessent or equivalent.\nStrong understanding of DFT timing constraints and physical implementation considerations.\n\nPreferred Skills:\nExperience in hierarchical and full-chip DFT implementation.\nExposure to boundary scan (JTAG), IEEE 1149.1 and IEEE 1500.\nKnowledge of Logic BIST (LBIST), OCC and ATPG pattern optimization.\nExperience working on advanced-node ASIC/SoC designs.\nUnderstanding of manufacturing test flows and silicon test requirements.\nSkills\nATPG, DFT, Design for Testability, MBIST, Tessent, TestMAX, TetraMAX","description_format":"text","description_chars":2192,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-10T09:35:30Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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