{"id":4045655,"url":"https://alion.io/job/leadsoc-technologies-verification-engineer","title":"Verification Engineer","company":{"id":3809842,"name":"LeadSoc Technologies","domain":"leadsoc.com","url":"https://alion.io/company/leadsoc-technologies-india","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-10T23:35:45Z","employer_posted_date":null,"last_verified_at":"2026-11-10T23:35:45Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"Key Responsibilities:\nDevelop and execute verification plans for complex IPs, subsystems, and SoCs based on design specifications and microarchitecture.\nBuild, enhance, and maintain reusable SystemVerilog/UVM verification environments.\nDevelop constrained-random and directed tests, sequences, drivers, monitors, and scoreboards.\nPerform functional verification of CPU designs or interfaces involving DDR, PCIe, Ethernet, or USB, depending on project requirements.\nDefine functional coverage models, analyze code and functional coverage, and drive coverage closure.\nDevelop assertions and protocol checkers to validate design behavior and identify corner-case issues.\nDebug simulation failures, identify root causes, and collaborate with design teams to resolve defects.\nManage regressions, track verification progress, and communicate risks and closure status.\nSupport integration, low-power verification, and gate-level simulation where applicable.\nParticipate in technical reviews and mentor junior engineers.\n\nRequired Skills & Qualifications:\nBachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.\n5+ years of hands-on experience in digital design verification.\nStrong proficiency in SystemVerilog and UVM, including testbench development and debugging.\nExperience with functional coverage, assertions, constrained-random verification, and coverage closure.\nHands-on experience with simulation and debug tools such as VCS, Questa, Xcelium, or Verdi.\nStrong understanding of digital design fundamentals and IP/subsystem/SoC verification methodologies.\nExpertise in one or more of the following domains:\nCPU Verification: Processor architecture, instruction execution, pipelines, interrupts, caches, coherency, and memory subsystems.\nDDR Verification: DDR/LPDDR concepts, initialization, memory transactions, timing requirements, and controller/interface verification.\nPCIe Verification: Transaction, data link, and physical-layer concepts; link training, configuration, error handling, and protocol compliance.\nEthernet Verification: MAC/PCS concepts, packet generation and checking, frame handling, flow control, and error scenarios.\nUSB Verification: USB protocol fundamentals, transfers, enumeration, endpoints, link behavior, and error handling.\n\nPreferred Skills:\nExperience integrating and debugging verification IP (VIP).\nKnowledge of AMBA protocols such as AXI, AHB, APB, or CHI.\nFamiliarity with scripting languages such as Python, Perl, or Shell.\nExposure to formal verification, emulation, or low-power verification.\nStrong analytical, communication, and stakeholder collaboration skills.\nSkills\nCPU, DDR, Ethernet, PCIE, SystemVerilog, USB, UVM","description_format":"text","description_chars":2722,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-10T23:35:45Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":29,"reasons":["seen:0","win:early"],"computed_at":"2026-11-11T03:01:11Z"},"pay":null,"html_url":"https://alion.io/job/leadsoc-technologies-verification-engineer","json_url":"https://alion.io/job/leadsoc-technologies-verification-engineer.json","meta":{"generated_at":"2026-11-11T03:01:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1810,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3809842},"rest":"https://alion.io/mcp/rest/get_company?id=3809842"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fleadsoc-technologies-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fleadsoc-technologies-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fleadsoc-technologies-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/leadsoc-technologies-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fleadsoc-technologies-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4045655}},{"tool":"search_jobs","arguments":{"company":"leadsoc.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4045655},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); 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Docs: https://alion.io/developers"}}